* [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init @ 2022-11-01 9:52 Vyacheslav Yurkov 2022-11-01 9:52 ` [PATCH 2/2] ARM: socfpga: Configure F2SDRAM bridges Vyacheslav Yurkov 2022-11-01 9:58 ` [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init Ahmad Fatoum 0 siblings, 2 replies; 5+ messages in thread From: Vyacheslav Yurkov @ 2022-11-01 9:52 UTC (permalink / raw) To: barebox; +Cc: Vyacheslav Yurkov From: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> Incorrect enable bits were used in initialization sequence of SDRAM firewall Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> --- arch/arm/mach-socfpga/arria10-sdram.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c index 35c355df71..b7eade0b17 100644 --- a/arch/arm/mach-socfpga/arria10-sdram.c +++ b/arch/arm/mach-socfpga/arria10-sdram.c @@ -486,7 +486,7 @@ static int arria10_sdram_firewall_setup(void) writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR); writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR); - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN; + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN; writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR); @@ -494,7 +494,7 @@ static int arria10_sdram_firewall_setup(void) writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR); writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR); - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN; + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN; writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR); @@ -502,7 +502,7 @@ static int arria10_sdram_firewall_setup(void) writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR); writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR); - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN; + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN; writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR); -- 2.25.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] ARM: socfpga: Configure F2SDRAM bridges 2022-11-01 9:52 [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init Vyacheslav Yurkov @ 2022-11-01 9:52 ` Vyacheslav Yurkov 2022-11-01 9:58 ` [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init Ahmad Fatoum 1 sibling, 0 replies; 5+ messages in thread From: Vyacheslav Yurkov @ 2022-11-01 9:52 UTC (permalink / raw) To: barebox; +Cc: Vyacheslav Yurkov From: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> When DDR firewall configuration is updated the F2SDRAM bridges need to be brought from reset. Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> --- arch/arm/mach-socfpga/arria10-sdram.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c index b7eade0b17..a6eb63299a 100644 --- a/arch/arm/mach-socfpga/arria10-sdram.c +++ b/arch/arm/mach-socfpga/arria10-sdram.c @@ -468,6 +468,18 @@ static void arria10_sdram_mmr_init(void) } } +static void arria10_f2sdram_bridges_reset(void) +{ + uint32_t val; + + /* Release F2SDRAM bridges from reset */ + val = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST); + val &= ~(ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0 | + ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1 | + ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2); + writel(val, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST); +} + static int arria10_sdram_firewall_setup(void) { uint32_t mpu_en = 0; @@ -512,6 +524,8 @@ static int arria10_sdram_firewall_setup(void) writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR); writel(ARRIA10_NOC_FW_DDR_L3_HPSREG0EN, ARRIA10_NOC_FW_DDR_L3_EN); + arria10_f2sdram_bridges_reset(); + return 0; } -- 2.25.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init 2022-11-01 9:52 [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init Vyacheslav Yurkov 2022-11-01 9:52 ` [PATCH 2/2] ARM: socfpga: Configure F2SDRAM bridges Vyacheslav Yurkov @ 2022-11-01 9:58 ` Ahmad Fatoum 2022-11-01 10:05 ` Vyacheslav Yurkov 1 sibling, 1 reply; 5+ messages in thread From: Ahmad Fatoum @ 2022-11-01 9:58 UTC (permalink / raw) To: Vyacheslav Yurkov, barebox; +Cc: Vyacheslav Yurkov Hello Slava, On 01.11.22 10:52, Vyacheslav Yurkov wrote: > From: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> > > Incorrect enable bits were used in initialization sequence of SDRAM > firewall Thanks for your patch. It'd be useful to know what implications the incorrect enable bits had. What didn't work that now does? Cheers, Ahmad > > Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> > --- > arch/arm/mach-socfpga/arria10-sdram.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c > index 35c355df71..b7eade0b17 100644 > --- a/arch/arm/mach-socfpga/arria10-sdram.c > +++ b/arch/arm/mach-socfpga/arria10-sdram.c > @@ -486,7 +486,7 @@ static int arria10_sdram_firewall_setup(void) > writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR); > writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR); > > - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN; > + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN; > writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); > > writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR); > @@ -494,7 +494,7 @@ static int arria10_sdram_firewall_setup(void) > writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR); > writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR); > > - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN; > + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN; > writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); > > writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR); > @@ -502,7 +502,7 @@ static int arria10_sdram_firewall_setup(void) > writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR); > writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR); > > - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN; > + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN; > writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); > > writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR); -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init 2022-11-01 9:58 ` [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init Ahmad Fatoum @ 2022-11-01 10:05 ` Vyacheslav Yurkov 2022-11-01 10:13 ` Ahmad Fatoum 0 siblings, 1 reply; 5+ messages in thread From: Vyacheslav Yurkov @ 2022-11-01 10:05 UTC (permalink / raw) To: Ahmad Fatoum, barebox; +Cc: Vyacheslav Yurkov Hi Ahmad, The access of FPGA IPs to SDRAM regions is now possible. The region filters were already set correctly, only 'enable' bits were not. I split the fix into two patches, because they fix different sub-problems of one issue. Regards, Slava On 01.11.2022 10:58, Ahmad Fatoum wrote: > Hello Slava, > > On 01.11.22 10:52, Vyacheslav Yurkov wrote: >> From: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> >> >> Incorrect enable bits were used in initialization sequence of SDRAM >> firewall > Thanks for your patch. > > It'd be useful to know what implications the incorrect enable bits had. > What didn't work that now does? > > Cheers, > Ahmad > >> Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> >> --- >> arch/arm/mach-socfpga/arria10-sdram.c | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c >> index 35c355df71..b7eade0b17 100644 >> --- a/arch/arm/mach-socfpga/arria10-sdram.c >> +++ b/arch/arm/mach-socfpga/arria10-sdram.c >> @@ -486,7 +486,7 @@ static int arria10_sdram_firewall_setup(void) >> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR); >> writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR); >> >> - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN; >> + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN; >> writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); >> >> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR); >> @@ -494,7 +494,7 @@ static int arria10_sdram_firewall_setup(void) >> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR); >> writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR); >> >> - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN; >> + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN; >> writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); >> >> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR); >> @@ -502,7 +502,7 @@ static int arria10_sdram_firewall_setup(void) >> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR); >> writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR); >> >> - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN; >> + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN; >> writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); >> >> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR); ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init 2022-11-01 10:05 ` Vyacheslav Yurkov @ 2022-11-01 10:13 ` Ahmad Fatoum 0 siblings, 0 replies; 5+ messages in thread From: Ahmad Fatoum @ 2022-11-01 10:13 UTC (permalink / raw) To: Vyacheslav Yurkov, barebox; +Cc: Vyacheslav Yurkov Hello Slava, On 01.11.22 11:05, Vyacheslav Yurkov wrote: > Hi Ahmad, > The access of FPGA IPs to SDRAM regions is now possible. The region filters were already set correctly, only 'enable' bits were not. I split the fix into two patches, because they fix different sub-problems of one issue. Thanks for the explanation. Could you resend with something like " This enables the FPGA to access regions of SDRAM, which were previously inaccessible. " appended to the commit message? Cheers, Ahmad > > Regards, > Slava > > On 01.11.2022 10:58, Ahmad Fatoum wrote: >> Hello Slava, >> >> On 01.11.22 10:52, Vyacheslav Yurkov wrote: >>> From: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> >>> >>> Incorrect enable bits were used in initialization sequence of SDRAM >>> firewall >> Thanks for your patch. >> >> It'd be useful to know what implications the incorrect enable bits had. >> What didn't work that now does? >> >> Cheers, >> Ahmad >> >>> Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> >>> --- >>> arch/arm/mach-socfpga/arria10-sdram.c | 6 +++--- >>> 1 file changed, 3 insertions(+), 3 deletions(-) >>> >>> diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c >>> index 35c355df71..b7eade0b17 100644 >>> --- a/arch/arm/mach-socfpga/arria10-sdram.c >>> +++ b/arch/arm/mach-socfpga/arria10-sdram.c >>> @@ -486,7 +486,7 @@ static int arria10_sdram_firewall_setup(void) >>> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR); >>> writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR); >>> - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN; >>> + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN; >>> writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); >>> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR); >>> @@ -494,7 +494,7 @@ static int arria10_sdram_firewall_setup(void) >>> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR); >>> writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR); >>> - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN; >>> + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN; >>> writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); >>> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR); >>> @@ -502,7 +502,7 @@ static int arria10_sdram_firewall_setup(void) >>> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR); >>> writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR); >>> - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN; >>> + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN; >>> writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); >>> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR); > > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-11-01 10:14 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-11-01 9:52 [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init Vyacheslav Yurkov 2022-11-01 9:52 ` [PATCH 2/2] ARM: socfpga: Configure F2SDRAM bridges Vyacheslav Yurkov 2022-11-01 9:58 ` [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init Ahmad Fatoum 2022-11-01 10:05 ` Vyacheslav Yurkov 2022-11-01 10:13 ` Ahmad Fatoum
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