* [PATCH 0/2] align rk356x drivers as preparation for mainline dts
@ 2022-05-09 11:36 Michael Riesch
2022-05-09 11:36 ` [PATCH 1/2] phy: rockchip: align naneng-combphy clocks and resets with binding Michael Riesch
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Michael Riesch @ 2022-05-09 11:36 UTC (permalink / raw)
To: barebox; +Cc: Frank Wunderlich, Michael Riesch
Hi all,
These patches align the barebox drivers for the Naneng Combo PHY and the dwc3
with the current device tree bindings in mainline Linux. Thereby, the
migration from the initial device tree files related to the RK3568 EVB1 and
the BananaPi R2Pro to their equivalents in mainline Linux is facilitated.
In order to ensure compatibility, the initial device tree files in
arch/arm/dts are adjusted accordingly.
The changes are tested exclusively on the RK3568 EVB1 -- Frank, if you could
give this a test on the BananaPi it would be great.
Looking forward to your comments!
Best regards,
Michael
Michael Riesch (2):
phy: rockchip: align naneng-combphy clocks and resets with binding
usb: dwc3: align dwc3 clocks with binding
arch/arm/dts/rk3568-bpi-r2-pro.dts | 7 +-
arch/arm/dts/rk3568-evb1-v10.dts | 14 ++--
arch/arm/dts/rk3568.dtsi | 82 +++++++------------
.../rockchip/phy-rockchip-naneng-combphy.c | 19 +----
drivers/usb/dwc3/core.c | 50 ++++++++---
5 files changed, 79 insertions(+), 93 deletions(-)
--
2.30.2
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] phy: rockchip: align naneng-combphy clocks and resets with binding
2022-05-09 11:36 [PATCH 0/2] align rk356x drivers as preparation for mainline dts Michael Riesch
@ 2022-05-09 11:36 ` Michael Riesch
2022-05-09 11:36 ` [PATCH 2/2] usb: dwc3: align dwc3 clocks " Michael Riesch
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Michael Riesch @ 2022-05-09 11:36 UTC (permalink / raw)
To: barebox; +Cc: Frank Wunderlich, Michael Riesch
There was no device tree binding in mainline Linux when this driver
was introduced in barebox. This has changed in the mean time, hence
we need to align the clocks and resets in this driver.
This step is a prerequisite for replacing the initial rk3568.dtsi in
arch/arm/dts with the mainline Linux version. For compatibility, the
former is updated accordingly.
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
arch/arm/dts/rk3568.dtsi | 10 ++++------
.../rockchip/phy-rockchip-naneng-combphy.c | 19 ++++---------------
2 files changed, 8 insertions(+), 21 deletions(-)
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index 0f19d3f0c0..28121dbdf3 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -367,11 +367,10 @@
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
<&cru PCLK_PIPE>;
- clock-names = "refclk", "apbclk", "pipe_clk";
+ clock-names = "ref", "apb", "pipe";
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
assigned-clock-rates = <24000000>;
- resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
- reset-names = "combphy-apb", "combphy";
+ resets = <&cru SRST_PIPEPHY0>;
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
status = "disabled";
@@ -383,11 +382,10 @@
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
<&cru PCLK_PIPE>;
- clock-names = "refclk", "apbclk", "pipe_clk";
+ clock-names = "ref", "apb", "pipe";
assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
assigned-clock-rates = <24000000>;
- resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
- reset-names = "combphy-apb", "combphy";
+ resets = <&cru SRST_PIPEPHY1>;
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
status = "disabled";
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 445703ecd8..2d86d86334 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -83,7 +83,6 @@ struct rockchip_combphy_priv {
struct regmap *pipe_grf;
struct regmap *phy_grf;
struct phy *phy;
- struct reset_control *apb_rst;
struct reset_control *phy_rst;
const struct rockchip_combphy_cfg *cfg;
};
@@ -317,17 +316,7 @@ static int rockchip_combphy_parse_dt(struct device_d *dev,
param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
true);
- priv->apb_rst = reset_control_get(dev, "combphy-apb");
- if (IS_ERR(priv->apb_rst)) {
- ret = PTR_ERR(priv->apb_rst);
-
- if (ret != -EPROBE_DEFER)
- dev_warn(dev, "failed to get apb reset\n");
-
- return ret;
- }
-
- priv->phy_rst = reset_control_get(dev, "combphy");
+ priv->phy_rst = reset_control_get(dev, NULL);
if (IS_ERR(priv->phy_rst)) {
ret = PTR_ERR(priv->phy_rst);
@@ -579,9 +568,9 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
};
static const struct clk_bulk_data rk3568_clks[] = {
- { .id = "refclk" },
- { .id = "apbclk" },
- { .id = "pipe_clk" },
+ { .id = "ref" },
+ { .id = "apb" },
+ { .id = "pipe" },
};
static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
--
2.30.2
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] usb: dwc3: align dwc3 clocks with binding
2022-05-09 11:36 [PATCH 0/2] align rk356x drivers as preparation for mainline dts Michael Riesch
2022-05-09 11:36 ` [PATCH 1/2] phy: rockchip: align naneng-combphy clocks and resets with binding Michael Riesch
@ 2022-05-09 11:36 ` Michael Riesch
2022-05-10 8:11 ` Aw: [PATCH 0/2] align rk356x drivers as preparation for mainline dts Frank Wunderlich
2022-05-11 6:28 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Michael Riesch @ 2022-05-09 11:36 UTC (permalink / raw)
To: barebox; +Cc: Frank Wunderlich, Michael Riesch
The device tree bindings snps,dwc3.yaml and rockchip,dwc3.yaml
specify different clock names. This inconsistency did not matter
in the past as the snps,dwc3 used to be a subnode of the
rockchip,rk3xyz-dwc3 glue node. For the RK356x, however, a
different approach is used and the two nodes are merged.
Therefore, the dwc3 driver must accept both groups of clock names.
This step is a prerequisite for replacing the initial rk3568.dtsi
in arch/arm/dts with the mainline Linux version. For compatibility,
the former is updated accordingly. This also illustrates the
migration from glue node and subnode to a single device tree node.
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
arch/arm/dts/rk3568-bpi-r2-pro.dts | 7 +--
arch/arm/dts/rk3568-evb1-v10.dts | 14 +++---
arch/arm/dts/rk3568.dtsi | 72 ++++++++++--------------------
drivers/usb/dwc3/core.c | 50 ++++++++++++++++-----
4 files changed, 71 insertions(+), 72 deletions(-)
diff --git a/arch/arm/dts/rk3568-bpi-r2-pro.dts b/arch/arm/dts/rk3568-bpi-r2-pro.dts
index db13f00cd0..da76ab64c1 100644
--- a/arch/arm/dts/rk3568-bpi-r2-pro.dts
+++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts
@@ -560,16 +560,13 @@
status = "okay";
};
-&usbdrd_dwc3 {
+&usb_host0_xhci {
dr_mode = "host";
extcon = <&usb2phy0>;
-};
-
-&usbdrd30 {
status = "okay";
};
-&usbhost30 {
+&usb_host1_xhci {
status = "okay";
};
diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
index 4ded9b1735..df5633978d 100644
--- a/arch/arm/dts/rk3568-evb1-v10.dts
+++ b/arch/arm/dts/rk3568-evb1-v10.dts
@@ -547,24 +547,20 @@
status = "okay";
};
-&usb_host1_ehci {
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
status = "okay";
};
-&usb_host1_ohci {
+&usb_host1_ehci {
status = "okay";
};
-&usbdrd_dwc3 {
- dr_mode = "otg";
- extcon = <&usb2phy0>;
-};
-
-&usbdrd30 {
+&usb_host1_ohci {
status = "okay";
};
-&usbhost30 {
+&usb_host1_xhci {
status = "okay";
};
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index 28121dbdf3..3c458754af 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -198,62 +198,38 @@
};
};
- usbdrd30: usbdrd {
- compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
+ usb_host0_xhci: usb@fcc00000 {
+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+ reg = <0x0 0xfcc00000 0x0 0x400000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
- <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>;
+ <&cru ACLK_USB3OTG0>;
clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "pipe_clk";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ "bus_clk";
+ dr_mode = "otg";
+ phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ resets = <&cru SRST_USB3OTG0>;
+ snps,dis_u2_susphy_quirk;
status = "disabled";
-
- usbdrd_dwc3: dwc3@fcc00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfcc00000 0x0 0x400000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "otg";
- phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- resets = <&cru SRST_USB3OTG0>;
- reset-names = "usb3-otg";
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,xhci-trb-ent-quirk;
- };
};
- usbhost30: usbhost {
- compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
+ usb_host1_xhci: usb@fd000000 {
+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+ reg = <0x0 0xfd000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
- <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>;
+ <&cru ACLK_USB3OTG1>;
clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "pipe_clk";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ "bus_clk";
+ dr_mode = "host";
+ phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ resets = <&cru SRST_USB3OTG1>;
+ snps,dis_u2_susphy_quirk;
status = "disabled";
-
- usbhost_dwc3: dwc3@fd000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfd000000 0x0 0x400000>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- resets = <&cru SRST_USB3OTG1>;
- reset-names = "usb3-host";
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,xhci-trb-ent-quirk;
- };
};
gic: interrupt-controller@fd400000 {
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index fd0ec754e0..30aaef90ac 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -23,6 +23,11 @@
#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
+struct dwc3_match_data {
+ const struct clk_bulk_data *clks;
+ const int num_clks;
+};
+
/**
* dwc3_get_dr_mode - Validates and sets dr_mode
* @dwc: pointer to our context structure
@@ -326,12 +331,6 @@ err0:
return ret;
}
-static const struct clk_bulk_data dwc3_core_clks[] = {
- { .id = "ref" },
- { .id = "bus_early" },
- { .id = "suspend" },
-};
-
/*
* dwc3_frame_length_adjustment - Adjusts frame length if required
* @dwc3: Pointer to our controller context structure
@@ -1098,20 +1097,23 @@ static void dwc3_coresoft_reset(struct dwc3 *dwc)
static int dwc3_probe(struct device_d *dev)
{
+ const struct dwc3_match_data *match;
struct dwc3 *dwc;
int ret;
dwc = xzalloc(sizeof(*dwc));
dev->priv = dwc;
- dwc->clks = xmemdup(dwc3_core_clks, sizeof(dwc3_core_clks));
+ match = device_get_match_data(dev);
+ dwc->clks = xmemdup(match->clks, match->num_clks *
+ sizeof(struct clk_bulk_data));
dwc->dev = dev;
dwc->regs = dev_get_mem_region(dwc->dev, 0) + DWC3_GLOBALS_REGS_START;
dwc3_get_properties(dwc);
if (dev->device_node) {
- dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
+ dwc->num_clks = match->num_clks;
if (of_find_property(dev->device_node, "clocks", NULL)) {
ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
@@ -1176,12 +1178,40 @@ static void dwc3_remove(struct device_d *dev)
clk_bulk_put(dwc->num_clks, dwc->clks);
}
+static const struct clk_bulk_data dwc3_core_clks[] = {
+ { .id = "ref" },
+ { .id = "bus_early" },
+ { .id = "suspend" },
+};
+
+static const struct dwc3_match_data dwc3_default = {
+ .clks = dwc3_core_clks,
+ .num_clks = ARRAY_SIZE(dwc3_core_clks),
+};
+
+static const struct clk_bulk_data dwc3_core_clks_rk3568[] = {
+ { .id = "ref_clk" },
+ { .id = "bus_clk" },
+ { .id = "suspend_clk" },
+};
+
+static const struct dwc3_match_data dwc3_rk3568 = {
+ .clks = dwc3_core_clks_rk3568,
+ .num_clks = ARRAY_SIZE(dwc3_core_clks_rk3568),
+};
+
static const struct of_device_id of_dwc3_match[] = {
{
- .compatible = "snps,dwc3"
+ .compatible = "snps,dwc3",
+ .data = &dwc3_default,
+ },
+ {
+ .compatible = "synopsys,dwc3",
+ .data = &dwc3_default,
},
{
- .compatible = "synopsys,dwc3"
+ .compatible = "rockchip,rk3568-dwc3",
+ .data = &dwc3_rk3568,
},
{ },
};
--
2.30.2
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Aw: [PATCH 0/2] align rk356x drivers as preparation for mainline dts
2022-05-09 11:36 [PATCH 0/2] align rk356x drivers as preparation for mainline dts Michael Riesch
2022-05-09 11:36 ` [PATCH 1/2] phy: rockchip: align naneng-combphy clocks and resets with binding Michael Riesch
2022-05-09 11:36 ` [PATCH 2/2] usb: dwc3: align dwc3 clocks " Michael Riesch
@ 2022-05-10 8:11 ` Frank Wunderlich
2022-05-11 6:28 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Frank Wunderlich @ 2022-05-10 8:11 UTC (permalink / raw)
To: Michael Riesch; +Cc: barebox, Michael Riesch
Hi,
> Gesendet: Montag, 09. Mai 2022 um 13:36 Uhr
> Von: "Michael Riesch" <michael.riesch@wolfvision.net>
> The changes are tested exclusively on the RK3568 EVB1 -- Frank, if you could
> give this a test on the BananaPi it would be great.
currently usb on r2pro v1 is broken in barebox. Have got it working for upper port and then applied this series.
It does not seem to break anything, upper port still working in my local repo (based on master).
> Looking forward to your comments!
>
> Best regards,
> Michael
regards Frank
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] align rk356x drivers as preparation for mainline dts
2022-05-09 11:36 [PATCH 0/2] align rk356x drivers as preparation for mainline dts Michael Riesch
` (2 preceding siblings ...)
2022-05-10 8:11 ` Aw: [PATCH 0/2] align rk356x drivers as preparation for mainline dts Frank Wunderlich
@ 2022-05-11 6:28 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2022-05-11 6:28 UTC (permalink / raw)
To: Michael Riesch; +Cc: barebox, Frank Wunderlich
On Mon, May 09, 2022 at 01:36:16PM +0200, Michael Riesch wrote:
> Hi all,
>
> These patches align the barebox drivers for the Naneng Combo PHY and the dwc3
> with the current device tree bindings in mainline Linux. Thereby, the
> migration from the initial device tree files related to the RK3568 EVB1 and
> the BananaPi R2Pro to their equivalents in mainline Linux is facilitated.
>
> In order to ensure compatibility, the initial device tree files in
> arch/arm/dts are adjusted accordingly.
>
> The changes are tested exclusively on the RK3568 EVB1 -- Frank, if you could
> give this a test on the BananaPi it would be great.
>
> Looking forward to your comments!
>
> Best regards,
> Michael
>
> Michael Riesch (2):
> phy: rockchip: align naneng-combphy clocks and resets with binding
> usb: dwc3: align dwc3 clocks with binding
Applied, thanks
Sascha
>
> arch/arm/dts/rk3568-bpi-r2-pro.dts | 7 +-
> arch/arm/dts/rk3568-evb1-v10.dts | 14 ++--
> arch/arm/dts/rk3568.dtsi | 82 +++++++------------
> .../rockchip/phy-rockchip-naneng-combphy.c | 19 +----
> drivers/usb/dwc3/core.c | 50 ++++++++---
> 5 files changed, 79 insertions(+), 93 deletions(-)
>
> --
> 2.30.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
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