[PATCH 5/9] arm: socfpga: agilex5: fix SDRAM size calculation

[Michael Tretter <m.tretter@pengutronix.de>]

The FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT is the upper limit of region 0,
which is a memory address instead of the size. Fix the calculation of
the SDRAM size by taking the SDRAM base address into consideration.

While at it, fix the function for memory addresses larger than 32 bits.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 include/mach/socfpga/soc64-sdram.h | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/include/mach/socfpga/soc64-sdram.h b/include/mach/socfpga/soc64-sdram.h
index 8f367822e869..c3eac2c43076 100644
--- a/include/mach/socfpga/soc64-sdram.h
+++ b/include/mach/socfpga/soc64-sdram.h
@@ -189,16 +189,29 @@ void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
 phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat);
 int agilex5_ddr_init_full(void);
 
-static inline resource_size_t agilex5_mpfe_sdram_size(void)
+static inline phys_addr_t agilex5_mpfe_sdram_base(void)
 {
 	u32 lower;
-	resource_size_t mem = 0;
+	u32 upper;
+
+	lower = FW_MPU_DDR_DMI0_SCR_READL(FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE);
+	upper = FW_MPU_DDR_DMI0_SCR_READL(FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT);
+
+	return ((u64)upper << 32) | lower;
+}
+
+static inline resource_size_t agilex5_mpfe_sdram_size(void)
+{
+	resource_size_t limit;
+	u32 lower;
+	u32 upper;
 
 	lower = FW_MPU_DDR_DMI0_SCR_READL(FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
+	upper = FW_MPU_DDR_DMI0_SCR_READL(FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 
-	mem = lower;
+	limit = ((u64)upper << 32) | lower;
 
-	return mem;
+	return limit - agilex5_mpfe_sdram_base() + 1;
 }
 
 #endif /* _SDRAM_SOC64_H_ */

-- 
2.47.3