[PATCH 7/9] arm: socfpga: agilex5: read SDRAM limits from firewall

[Michael Tretter <m.tretter@pengutronix.de>]

The hard-coded membase and memsize are not flexible enough for the
configurable SDRAM setup on Agilex 5.

The SZ_1M offset is the result of reserving some memory for the TF-A.
The offset isn't correct anymore, if the reserved area for the TF-A is
changed.

The memory size may change, if the EMIF is configured with inline ECC,
which reserves 1/8 of the memory for checksums and reduces the usable
SDRAM size. Depending on the EMIF configuration, the same board may or
may not use inline ECC.

Since the PBL in EL3 configures the firewall to consider the reserved
area for the TF-A and the reserved memory for ECC checksums, the PBL in
EL1 may read back the configuration to determine the usable memory for
barebox proper.

Add sanity checks on the base address and size to ensure the firewall is
actually configured.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
index 41c1b832a682..4817b3ec2d86 100644
--- a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
+++ b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
@@ -21,6 +21,8 @@ extern char __dtb_z_socfpga_agilex5_axe5_eagle_start[];
 static noinline void axe5_eagle_continue(void)
 {
 	void *fdt;
+	phys_addr_t membase;
+	phys_size_t memsize;
 
 	agilex5_clk_init();
 
@@ -68,7 +70,15 @@ static noinline void axe5_eagle_continue(void)
 
 	fdt = __dtb_z_socfpga_agilex5_axe5_eagle_start;
 
-	barebox_arm_entry(SOCFPGA_AGILEX5_DDR_BASE + SZ_1M, SZ_1G - SZ_1M, fdt);
+	membase = agilex5_mpfe_sdram_base();
+	memsize = agilex5_mpfe_sdram_size();
+
+	if (membase < SOCFPGA_AGILEX5_DDR_BASE || memsize == 0) {
+		pr_err("Invalid firewall configuration\n");
+		hang();
+	}
+
+	barebox_arm_entry(membase, memsize, fdt);
 }
 
 ENTRY_FUNCTION_WITHSTACK(start_socfpga_agilex5_axe5_eagle, AXE5_STACKTOP, r0, r1, r2)

-- 
2.47.3