[PATCH 22/27] ARM: pxa: add a barebox update handler for NAND

[Sascha Hauer <s.hauer@pengutronix.de>]

The PXA3xx Boot ROM boots from the start of the flash: an NTIM header,
the OBM it copies into internal SRAM and the image the OBM loads into
DRAM, all in one blob built by scripts/pxa-image. Add an update handler
that writes such a blob to the mtd partition covering it, so a board can
replace its own bootloader with barebox_update.

bbu_register_std_file_update() would do the copy, but it goes through
the cdev and writes straight over a bad block. Use mtd_peb_write_file()
instead, which skips them, so what lands in flash is the image with the
bad blocks taken out of it. That is what the other end expects:
pxa_nand_load_image() reads the flash offsets in the NTIM as offsets into
the good blocks and skips the bad ones the same way. The NTIM and the OBM
are in the first erase block, which cannot be bad, so the Boot ROM -
which knows nothing of any of this - always finds them where it looks.

The image is checked for filetype_pxa_ntim before anything is erased.
Writing something else to this partition leaves a board that only JTAG
can talk to.

Assisted-by: Claude Opus 5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-pxa/Kconfig  |  9 +++++
 arch/arm/mach-pxa/Makefile |  1 +
 arch/arm/mach-pxa/bbu.c    | 96 ++++++++++++++++++++++++++++++++++++++++++++++
 include/mach/pxa/bbu.h     | 18 +++++++++
 4 files changed, 124 insertions(+)

diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 5bc99f1f83..b159cee0cc 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -19,4 +19,13 @@ config ARCH_PXA310
 	bool
 	select ARCH_PXA3XX
 
+config BAREBOX_UPDATE_PXA_NAND
+	prompt "barebox update NAND handler"
+	bool
+	depends on ARCH_PXA3XX && BAREBOX_UPDATE && MTD
+	help
+	  Say Y here for an update handler that writes the image built by
+	  scripts/pxa-image - the NTIM header, the OBM and barebox - to the
+	  mtd partition the Boot ROM boots from.
+
 endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 4069a47251..86d9c4ca95 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -6,5 +6,6 @@ obj-y += common.o
 obj-y += devices.o
 
 obj-$(CONFIG_ARCH_PXA3XX) += mfp-pxa3xx.o pxa3xx.o
+obj-$(CONFIG_BAREBOX_UPDATE_PXA_NAND) += bbu.o
 
 pbl-$(CONFIG_ARCH_PXA3XX) += xload-nand.o
diff --git a/arch/arm/mach-pxa/bbu.c b/arch/arm/mach-pxa/bbu.c
new file mode 100644
index 0000000000..981069a016
--- /dev/null
+++ b/arch/arm/mach-pxa/bbu.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * barebox update handler for the PXA3xx NAND boot partition.
+ */
+
+#include <common.h>
+#include <bbu.h>
+#include <filetype.h>
+#include <fs.h>
+#include <malloc.h>
+#include <linux/err.h>
+#include <linux/mtd/mtd.h>
+#include <mtd/mtd-peb.h>
+#include <mach/pxa/bbu.h>
+
+static int pxa_bbu_nand_handler(struct bbu_handler *handler,
+				struct bbu_data *data)
+{
+	struct mtd_info *mtd;
+	struct cdev *cdev;
+	int ret;
+
+	/*
+	 * The Boot ROM expects an NTIM header at the start of the boot
+	 * device. Writing anything else here leaves a board that only JTAG
+	 * can talk to.
+	 */
+	if (file_detect_type(data->image, data->len) != filetype_pxa_ntim) {
+		if (!bbu_force(data, "%s is not a PXA3xx NTIM image",
+			       data->imagefile))
+			return -EINVAL;
+	}
+
+	cdev = cdev_by_name(devpath_to_name(data->devicefile));
+	if (!cdev) {
+		pr_err("%s: no such device\n", data->devicefile);
+		return -ENODEV;
+	}
+
+	mtd = cdev->mtd;
+	if (!mtd) {
+		pr_err("%s is not a mtd device\n", data->devicefile);
+		return -EINVAL;
+	}
+
+	/* last chance before erasing the flash */
+	ret = bbu_confirm(data);
+	if (ret)
+		return ret;
+
+	ret = mtd_peb_write_file(mtd, 0, mtd_num_pebs(mtd), data->image,
+				 data->len);
+	if (ret == -ENOSPC)
+		pr_err("%s holds %llu bytes, the image needs %zu\n",
+		       data->devicefile, mtd->size, data->len);
+
+	return ret;
+}
+
+/**
+ * pxa_bbu_nand_register_handler - register a NAND update handler
+ * @name:	Name of the handler
+ * @devicefile:	the mtd partition the Boot ROM boots from
+ *
+ * Registers an update handler for the image built by scripts/pxa-image: the
+ * NTIM header the Boot ROM reads, the OBM it copies into internal SRAM, and
+ * the barebox image the OBM loads into DRAM.
+ *
+ * Unlike bbu_register_std_file_update() this goes through
+ * mtd_peb_write_file(), so a factory bad block in the boot partition is
+ * skipped rather than written to, and what lands in flash is the image with
+ * the bad blocks taken out of it. That is what the other side expects:
+ * pxa_nand_load_image() reads the flash offsets in the NTIM as offsets into
+ * the good blocks and skips the bad ones the same way. The NTIM and the OBM
+ * are in the first erase block, which cannot be bad, so the Boot ROM - which
+ * has no idea about any of this - always finds them where it looks.
+ *
+ * Return: 0 if successful, negative error code otherwise
+ */
+int pxa_bbu_nand_register_handler(const char *name, const char *devicefile)
+{
+	struct bbu_handler *handler;
+	int ret;
+
+	handler = xzalloc(sizeof(*handler));
+	handler->devicefile = devicefile;
+	handler->name = name;
+	handler->handler = pxa_bbu_nand_handler;
+	handler->flags = BBU_HANDLER_FLAG_DEFAULT;
+
+	ret = bbu_register_handler(handler);
+	if (ret)
+		free(handler);
+
+	return ret;
+}
diff --git a/include/mach/pxa/bbu.h b/include/mach/pxa/bbu.h
new file mode 100644
index 0000000000..7b13009cf4
--- /dev/null
+++ b/include/mach/pxa/bbu.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MACH_PXA_BBU_H
+#define __MACH_PXA_BBU_H
+
+#include <bbu.h>
+
+#ifdef CONFIG_BAREBOX_UPDATE_PXA_NAND
+int pxa_bbu_nand_register_handler(const char *name, const char *devicefile);
+#else
+static inline int pxa_bbu_nand_register_handler(const char *name,
+						const char *devicefile)
+{
+	return 0;
+}
+#endif
+
+#endif /* __MACH_PXA_BBU_H */

-- 
2.47.3