[PATCH 08/27] mtd: nand: nand_mrvl_nfc: honour marvell,nand-keep-config

[Sascha Hauer <s.hauer@pengutronix.de>]

The property was parsed into host->keep_config and then never looked at,
so the driver always recalculated the timings from the core clock rate,
even where the device tree explicitly says not to.

Honour it. Where it is set, the timings the previous stage left behind
are known to work, and the driver no longer depends on clk_get_rate()
returning anything accurate for the NAND controller clock.

Assisted-by: Claude Opus 5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/raw/nand_mrvl_nfc.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/nand_mrvl_nfc.c b/drivers/mtd/nand/raw/nand_mrvl_nfc.c
index 0e2a2b639a..6f3fb57062 100644
--- a/drivers/mtd/nand/raw/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/raw/nand_mrvl_nfc.c
@@ -343,11 +343,20 @@ static struct mrvl_nand_timing timings[] = {
 static void mrvl_nand_set_timing(struct mrvl_nand_host *host, bool use_default)
 {
 	struct nand_chip *chip = &host->chip;
-	unsigned long nand_clk = clk_get_rate(host->core_clk);
 	struct mrvl_nand_timing *t;
+	unsigned long nand_clk;
 	uint32_t ndtr0, ndtr1;
 	u16 id;
 
+	/*
+	 * The previous stage has set up timings that are known to work,
+	 * keep them instead of calculating our own.
+	 */
+	if (host->keep_config)
+		return;
+
+	nand_clk = clk_get_rate(host->core_clk);
+
 	if (use_default) {
 		id = 0;
 	} else {

-- 
2.47.3