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* [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon
@ 2021-05-25  7:19 Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree Antony Pavlov
                   ` (10 more replies)
  0 siblings, 11 replies; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

Changes since v2:

  * rebase on top of master branch (f873c7ff2497) +
    "RISC-V: extend multi-image to support both S- and M-Mode"
    (http://lists.infradead.org/pipermail/barebox/2021-May/036086.html).
  * "litex serial: add setbrg callback" patch by Marek Czerski is added
    for review;
  * fix "clocksource: timer-riscv: select CSR from device tree" patch;
  * change gpio IP-block base addresses in litex dts;
  * gpio-74xx-mmio uses device_get_match_data() now.

Changes since v1:

  * rebased on top of next branch;
  * new patches are introduced:
    * clocksource: timer-riscv: select CSR from device tree
    * RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive
    * RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n
  * almost all of Ahmad's notes are fixed (e.g. unused header files inclusions are dropped);
  * NOT FIXED: gpio-74xx-mmio still uses dev_get_drvdata(), not device_get_match_data()

Antony Pavlov (9):
  clocksource: timer-riscv: select CSR from device tree
  RISC-V: make it possible to run nmon from PBL C code
  RISC-V: boards: erizo: make it possible to use nmon
  serial: add litex UART driver
  gpio: add driver for 74xx-ICs with MMIO access
  spi: add litex spiflash driver
  net: add LiteEth driver
  RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
  RISC-V: add litex_linux_defconfig

Marek Czerski (1):
  litex serial: add setbrg callback

 arch/riscv/Kconfig.socs                  |  14 +
 arch/riscv/boards/Makefile               |   1 +
 arch/riscv/boards/erizo/lowlevel.c       |   4 +
 arch/riscv/boards/litex-linux/Makefile   |   3 +
 arch/riscv/boards/litex-linux/lowlevel.c |  22 ++
 arch/riscv/boot/Makefile                 |   1 +
 arch/riscv/boot/nmon_entry.S             |  13 +
 arch/riscv/configs/litex_linux_defconfig |  76 +++++
 arch/riscv/dts/Makefile                  |   1 +
 arch/riscv/dts/erizo.dtsi                |   2 +
 arch/riscv/dts/litex-linux.dts           |  92 ++++++
 arch/riscv/dts/litex_soc_linux.dtsi      |  49 +++
 arch/riscv/include/asm/debug_ll.h        |   3 +
 arch/riscv/include/asm/debug_ll_litex.h  | 123 ++++++++
 arch/riscv/include/asm/riscv_nmon.h      |  49 ++-
 common/Kconfig                           |   4 +
 drivers/clocksource/timer-riscv.c        |  24 +-
 drivers/gpio/Kconfig                     |  14 +
 drivers/gpio/Makefile                    |   1 +
 drivers/gpio/gpio-74xx-mmio.c            | 165 ++++++++++
 drivers/net/Kconfig                      |   8 +
 drivers/net/Makefile                     |   1 +
 drivers/net/liteeth.c                    | 376 +++++++++++++++++++++++
 drivers/serial/Makefile                  |   1 +
 drivers/serial/serial_litex.c            | 103 +++++++
 drivers/spi/Kconfig                      |   3 +
 drivers/spi/Makefile                     |   1 +
 drivers/spi/litex_spiflash.c             | 241 +++++++++++++++
 images/Makefile.riscv                    |   4 +
 29 files changed, 1370 insertions(+), 29 deletions(-)
 create mode 100644 arch/riscv/boards/litex-linux/Makefile
 create mode 100644 arch/riscv/boards/litex-linux/lowlevel.c
 create mode 100644 arch/riscv/boot/nmon_entry.S
 create mode 100644 arch/riscv/configs/litex_linux_defconfig
 create mode 100644 arch/riscv/dts/litex-linux.dts
 create mode 100644 arch/riscv/dts/litex_soc_linux.dtsi
 create mode 100644 arch/riscv/include/asm/debug_ll_litex.h
 create mode 100644 drivers/gpio/gpio-74xx-mmio.c
 create mode 100644 drivers/net/liteeth.c
 create mode 100644 drivers/serial/serial_litex.c
 create mode 100644 drivers/spi/litex_spiflash.c

-- 
2.31.1


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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-05-25 12:54   ` Ahmad Fatoum
  2021-05-25  7:19 ` [PATCH v3 02/10] RISC-V: make it possible to run nmon from PBL C code Antony Pavlov
                   ` (9 subsequent siblings)
  10 siblings, 1 reply; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

barebox timer-riscv driver supports one of user counters:

  * 'cycle', counter for RDCYCLE instruction (CSR 0xc00);
  * 'time', timer for RDTIME instruction (CSR 0xc01).

At the moment in M-mode timer-riscv uses the 'cycle' counter,
and in S-mode timer-riscv uses the 'time' timer.

Alas picorv32 CPU core supports only the 'cycle' counter.
VexRiscV CPU core in M-mode supports only the 'time' timer.

This patch makes it possible to use the 'time' timer
for VexRiscV CPU in M-mode.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/riscv/dts/erizo.dtsi         |  2 ++
 drivers/clocksource/timer-riscv.c | 24 ++++++++++++------------
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi
index 228711bd69..4eb92ae6f1 100644
--- a/arch/riscv/dts/erizo.dtsi
+++ b/arch/riscv/dts/erizo.dtsi
@@ -22,6 +22,8 @@
 
 		timebase-frequency = <24000000>;
 
+		barebox,csr-cycle;
+
 		cpu@0 {
 			device_type = "cpu";
 			compatible = "cliffordwolf,picorv32", "riscv";
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index cbbe18d9a6..305d1ecea0 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -12,9 +12,8 @@
 #include <clock.h>
 #include <asm/timer.h>
 #include <asm/csr.h>
-#include <asm/system.h>
 
-static u64 notrace riscv_timer_get_count_sbi(void)
+static u64 notrace riscv_timer_get_count_time(void)
 {
 	__maybe_unused u32 hi, lo;
 
@@ -29,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void)
 	return ((u64)hi << 32) | lo;
 }
 
-static u64 notrace riscv_timer_get_count_rdcycle(void)
+static u64 notrace riscv_timer_get_count_cycle(void)
 {
 	__maybe_unused u32 hi, lo;
 
@@ -44,24 +43,25 @@ static u64 notrace riscv_timer_get_count_rdcycle(void)
 	return ((u64)hi << 32) | lo;
 }
 
-static u64 notrace riscv_timer_get_count(void)
-{
-	if (riscv_mode() == RISCV_S_MODE)
-		return riscv_timer_get_count_sbi();
-	else
-		return riscv_timer_get_count_rdcycle();
-}
-
 static struct clocksource riscv_clocksource = {
-	.read		= riscv_timer_get_count,
 	.mask		= CLOCKSOURCE_MASK(64),
 	.priority	= 100,
 };
 
 static int riscv_timer_init(struct device_d* dev)
 {
+	struct device_node *cpu;
+
 	dev_info(dev, "running at %lu Hz\n", riscv_timebase);
 
+	cpu = of_find_node_by_path("/cpus");
+
+	if (of_property_read_bool(cpu, "barebox,csr-cycle")) {
+		riscv_clocksource.read = riscv_timer_get_count_cycle;
+	} else {
+		riscv_clocksource.read = riscv_timer_get_count_time;
+	}
+
 	riscv_clocksource.mult = clocksource_hz2mult(riscv_timebase, riscv_clocksource.shift);
 
 	return init_clock(&riscv_clocksource);
-- 
2.31.1


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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 02/10] RISC-V: make it possible to run nmon from PBL C code
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 03/10] RISC-V: boards: erizo: make it possible to use nmon Antony Pavlov
                   ` (8 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

After migrating to PBL we can't use nmon assembler macro
in C code anymore. Some changes are introduced to invoke
nmon from PBL C code:

  * use 'lla' macro instruction instead of 'la';
  * don't touch the 'ra' register, use 'a2' instead;
  * add wrapper C function for nmon.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/riscv/boot/Makefile            |  1 +
 arch/riscv/boot/nmon_entry.S        | 13 ++++++++
 arch/riscv/include/asm/riscv_nmon.h | 49 +++++++++++++++++++----------
 3 files changed, 46 insertions(+), 17 deletions(-)

diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
index 968a826d16..80f63a4a0a 100644
--- a/arch/riscv/boot/Makefile
+++ b/arch/riscv/boot/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-y += start.o
 pbl-y += entry.o uncompress.o
+pbl-y += nmon_entry.o
 pbl-$(CONFIG_BOARD_GENERIC_DT) += board-dt-2nd.o
diff --git a/arch/riscv/boot/nmon_entry.S b/arch/riscv/boot/nmon_entry.S
new file mode 100644
index 0000000000..ae017d2a1c
--- /dev/null
+++ b/arch/riscv/boot/nmon_entry.S
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <linux/linkage.h>
+#include <asm/sections.h>
+
+#include "asm/debug_ll.h"
+#include "asm/riscv_nmon.h"
+
+.section .text_bare_init
+
+ENTRY(__barebox_nmon_entry)
+	riscv_nmon
+	ret
+ENDPROC(__barebox_nmon_entry)
diff --git a/arch/riscv/include/asm/riscv_nmon.h b/arch/riscv/include/asm/riscv_nmon.h
index caf213cdd8..8a44e216d7 100644
--- a/arch/riscv/include/asm/riscv_nmon.h
+++ b/arch/riscv/include/asm/riscv_nmon.h
@@ -16,13 +16,26 @@
 #ifndef __ASM_RISCV_NMON_H
 #define __ASM_RISCV_NMON_H
 
+#include <linux/kconfig.h>
+
 #define CODE_ESC	0x1b
 
+#ifndef __ASSEMBLY__
+
+extern void __barebox_nmon_entry(void);
+
+static inline void barebox_nmon_entry(void)
+{
+	if (IS_ENABLED(CONFIG_NMON))
+		__barebox_nmon_entry();
+}
+
+#else
+
 .macro nmon_outs msg
 
-	la	a1, \msg
-
-	jal	_nmon_outs
+	lla	a1, \msg
+	jal	a2, _nmon_outs
 
 .endm
 
@@ -73,7 +86,7 @@ nmon_main:
 	li	a0, 'q'
 	bne	s0, a0, 3f
 
-	jal	_nmon_outc_a0
+	jal	a2, _nmon_outc_a0
 
 	j	nmon_exit
 
@@ -90,12 +103,12 @@ nmon_main:
 	j	nmon_main_help
 
 nmon_cmd_d:
-	jal	_nmon_outc_a0
+	jal	a2, _nmon_outc_a0
 
 	li	a0, ' '
-	jal	_nmon_outc_a0
+	jal	a2, _nmon_outc_a0
 
-	jal	_nmon_gethexw
+	jal	a2, _nmon_gethexw
 
 	nmon_outs	msg_nl
 
@@ -105,28 +118,28 @@ nmon_cmd_d:
 	j	nmon_main
 
 nmon_cmd_w:
-	jal	_nmon_outc_a0
+	jal	a2, _nmon_outc_a0
 
 	li	a0, ' '
-	jal	_nmon_outc_a0
+	jal	a2, _nmon_outc_a0
 
-	jal	_nmon_gethexw
+	jal	a2, _nmon_gethexw
 	move	s2, s0
 
 	li	a0, ' '
-	jal	_nmon_outc_a0
-	jal	_nmon_gethexw
+	jal	a2, _nmon_outc_a0
+	jal	a2, _nmon_gethexw
 
 	sw	s0, 0(s2)
 	j	nmon_main
 
 nmon_cmd_g:
-	jal	_nmon_outc_a0
+	jal	a2, _nmon_outc_a0
 
 	li	a0, ' '
-	jal	_nmon_outc_a0
+	jal	a2, _nmon_outc_a0
 
-	jal	_nmon_gethexw
+	jal	a2, _nmon_gethexw
 	move	s2, s0
 
 	nmon_outs	msg_nl
@@ -136,7 +149,7 @@ nmon_cmd_g:
 
 _nmon_outc_a0:
 	debug_ll_outc_a0
-	jr	ra
+	jr	a2
 
 _nmon_outs:
 
@@ -202,7 +215,7 @@ _get_hex_digit:
 	move	s0, t2
 
 _nmon_jr_ra_exit:
-	jr	ra
+	jr	a2
 
 msg_prompt:
 	.asciz "\r\nnmon> "
@@ -231,4 +244,6 @@ nmon_exit:
 
 .endm
 
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_RISCV_NMON_H */
-- 
2.31.1


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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 03/10] RISC-V: boards: erizo: make it possible to use nmon
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 02/10] RISC-V: make it possible to run nmon from PBL C code Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 04/10] serial: add litex UART driver Antony Pavlov
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/riscv/boards/erizo/lowlevel.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/boards/erizo/lowlevel.c b/arch/riscv/boards/erizo/lowlevel.c
index fc262ed61b..e75a87466a 100644
--- a/arch/riscv/boards/erizo/lowlevel.c
+++ b/arch/riscv/boards/erizo/lowlevel.c
@@ -3,6 +3,7 @@
 #include <common.h>
 #include <asm/barebox-riscv.h>
 #include <debug_ll.h>
+#include <asm/riscv_nmon.h>
 
 ENTRY_FUNCTION(start_erizo_generic, a0, a1, a2)
 {
@@ -10,6 +11,9 @@ ENTRY_FUNCTION(start_erizo_generic, a0, a1, a2)
 	void *fdt;
 
 	debug_ll_init();
+
+	barebox_nmon_entry();
+
 	putc_ll('>');
 
 	/* On POR, we are running from read-only memory here. */
-- 
2.31.1


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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 04/10] serial: add litex UART driver
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
                   ` (2 preceding siblings ...)
  2021-05-25  7:19 ` [PATCH v3 03/10] RISC-V: boards: erizo: make it possible to use nmon Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 05/10] litex serial: add setbrg callback Antony Pavlov
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 drivers/serial/Makefile       |  1 +
 drivers/serial/serial_litex.c | 96 +++++++++++++++++++++++++++++++++++
 2 files changed, 97 insertions(+)

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 5120b17376..45055371ea 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_DRIVER_SERIAL_DIGIC)		+= serial_digic.o
 obj-$(CONFIG_DRIVER_SERIAL_LPUART)		+= serial_lpuart.o
 obj-$(CONFIG_VIRTIO_CONSOLE)			+= virtio_console.o
 obj-$(CONFIG_SERIAL_SIFIVE)			+= serial_sifive.o
+obj-$(CONFIG_SOC_LITEX)				+= serial_litex.o
diff --git a/drivers/serial/serial_litex.c b/drivers/serial/serial_litex.c
new file mode 100644
index 0000000000..8562a45ecc
--- /dev/null
+++ b/drivers/serial/serial_litex.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+
+#define UART_RXTX	0x00
+#define UART_TXFULL	0x04
+#define UART_RXEMPTY	0x08
+#define UART_EV_PENDING	0x10
+#define  UART_EV_RX	(1 << 1)
+
+static inline uint32_t litex_serial_readb(struct console_device *cdev,
+						uint32_t offset)
+{
+	void __iomem *base = cdev->dev->priv;
+
+	return readb(base + offset);
+}
+
+static inline void litex_serial_writeb(struct console_device *cdev,
+					uint32_t value, uint32_t offset)
+{
+	void __iomem *base = cdev->dev->priv;
+
+	writeb(value, base + offset);
+}
+
+static void litex_serial_putc(struct console_device *cdev, char c)
+{
+	while (litex_serial_readb(cdev, UART_TXFULL))
+		;
+
+	litex_serial_writeb(cdev, c, UART_RXTX);
+}
+
+static int litex_serial_getc(struct console_device *cdev)
+{
+	int c;
+
+	while (litex_serial_readb(cdev, UART_RXEMPTY))
+		;
+
+	c = litex_serial_readb(cdev, UART_RXTX);
+
+	/* refresh UART_RXEMPTY by writing UART_EV_RX to UART_EV_PENDING */
+	litex_serial_writeb(cdev, UART_EV_RX, UART_EV_PENDING);
+
+	return c;
+}
+
+static int litex_serial_tstc(struct console_device *cdev)
+{
+	return !litex_serial_readb(cdev, UART_RXEMPTY);
+}
+
+static int litex_serial_probe(struct device_d *dev)
+{
+	struct resource *iores;
+	struct console_device *cdev;
+
+	cdev = xzalloc(sizeof(struct console_device));
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
+
+	dev->priv = IOMEM(iores->start);
+	cdev->dev = dev;
+	cdev->tstc = &litex_serial_tstc;
+	cdev->putc = &litex_serial_putc;
+	cdev->getc = &litex_serial_getc;
+	cdev->setbrg = NULL;
+
+	console_register(cdev);
+
+	return 0;
+}
+
+static __maybe_unused struct of_device_id litex_serial_dt_ids[] = {
+	{
+		.compatible = "litex,uart",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct driver_d litex_serial_driver = {
+	.name  = "litex-uart",
+	.probe = litex_serial_probe,
+	.of_compatible = DRV_OF_COMPAT(litex_serial_dt_ids),
+};
+console_platform_driver(litex_serial_driver);
-- 
2.31.1


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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 05/10] litex serial: add setbrg callback
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
                   ` (3 preceding siblings ...)
  2021-05-25  7:19 ` [PATCH v3 04/10] serial: add litex UART driver Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-05-25  7:36   ` Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 06/10] gpio: add driver for 74xx-ICs with MMIO access Antony Pavlov
                   ` (5 subsequent siblings)
  10 siblings, 1 reply; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Marek Czerski, Ahmad Fatoum

From: Marek Czerski <m.czerski@ap-tech.pl>

setbrg callback (set baudrate) is needed by the loadx/loady commands.
Because litex serial has fixed baudrate the callback only checks if
the requested baudrate is the same as the CONFIG_BAUDRATE.
---
 drivers/serial/serial_litex.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_litex.c b/drivers/serial/serial_litex.c
index 8562a45ecc..9d35a6e44a 100644
--- a/drivers/serial/serial_litex.c
+++ b/drivers/serial/serial_litex.c
@@ -58,6 +58,13 @@ static int litex_serial_tstc(struct console_device *cdev)
 	return !litex_serial_readb(cdev, UART_RXEMPTY);
 }
 
+static int litex_setial_setbaudrate(struct console_device *cdev, int baudrate)
+{
+	if (baudrate != CONFIG_BAUDRATE)
+		return -EINVAL;
+	return 0;
+}
+
 static int litex_serial_probe(struct device_d *dev)
 {
 	struct resource *iores;
@@ -73,7 +80,7 @@ static int litex_serial_probe(struct device_d *dev)
 	cdev->tstc = &litex_serial_tstc;
 	cdev->putc = &litex_serial_putc;
 	cdev->getc = &litex_serial_getc;
-	cdev->setbrg = NULL;
+	cdev->setbrg = &litex_setial_setbaudrate;
 
 	console_register(cdev);
 
-- 
2.31.1


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 06/10] gpio: add driver for 74xx-ICs with MMIO access
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
                   ` (4 preceding siblings ...)
  2021-05-25  7:19 ` [PATCH v3 05/10] litex serial: add setbrg callback Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 07/10] spi: add litex spiflash driver Antony Pavlov
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum, Alexander Shiyan

This patch adds driver to support GPIO functionality
for 74xx-compatible ICs with MMIO access.

Compatible models include:
     1 bit:   741G125 (Input), 741G74 (Output)
     2 bits:  742G125 (Input), 7474 (Output)
     4 bits:  74125 (Input), 74175 (Output)
     6 bits:  74365 (Input), 74174 (Output)
     8 bits:  74244 (Input), 74273 (Output)
     16 bits: 741624 (Input), 7416374 (Output)

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alexander Shiyan <shc_work@mail.ru>
---
 drivers/gpio/Kconfig          |  14 +++
 drivers/gpio/Makefile         |   1 +
 drivers/gpio/gpio-74xx-mmio.c | 165 ++++++++++++++++++++++++++++++++++
 3 files changed, 180 insertions(+)

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index a8ee9e58b8..579d5c04b3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -21,6 +21,20 @@ config GPIO_74164
 	  shift registers. This driver can be used to provide access
 	  to more gpio outputs.
 
+config GPIO_74XX_MMIO
+	tristate "GPIO driver for 74xx-ICs with MMIO access"
+	depends on OFDEVICE
+	select GPIO_GENERIC
+	help
+	  Say yes here to support GPIO functionality for 74xx-compatible ICs
+	  with MMIO access. Compatible models include:
+	    1 bit:	741G125 (Input), 741G74 (Output)
+	    2 bits:	742G125 (Input), 7474 (Output)
+	    4 bits:	74125 (Input), 74175 (Output)
+	    6 bits:	74365 (Input), 74174 (Output)
+	    8 bits:	74244 (Input), 74273 (Output)
+	    16 bits:	741624 (Input), 7416374 (Output)
+
 config GPIO_CLPS711X
 	bool "GPIO support for CLPS711X"
 	depends on ARCH_CLPS711X || COMPILE_TEST
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 25e12105d8..41c65fa0ac 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -1,6 +1,7 @@
 obj-$(CONFIG_GPIOLIB)		+= gpiolib.o
 
 obj-$(CONFIG_GPIO_74164)	+= gpio-74164.o
+obj-$(CONFIG_GPIO_74XX_MMIO)	+= gpio-74xx-mmio.o
 obj-$(CONFIG_MACH_MIPS_ATH79)	+= gpio-ath79.o
 obj-$(CONFIG_GPIO_DAVINCI)	+= gpio-davinci.o
 obj-$(CONFIG_GPIO_CLPS711X)	+= gpio-clps711x.o
diff --git a/drivers/gpio/gpio-74xx-mmio.c b/drivers/gpio/gpio-74xx-mmio.c
new file mode 100644
index 0000000000..5b688f4766
--- /dev/null
+++ b/drivers/gpio/gpio-74xx-mmio.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * 74xx MMIO GPIO driver
+ *
+ *  Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * Ported to barebox from linux-v5.4-rc6
+ *   Copyright (C) 2019-2021 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <errno.h>
+#include <gpio.h>
+#include <init.h>
+#include <io.h>
+#include <malloc.h>
+#include <of_device.h>
+
+#include <linux/err.h>
+#include <linux/basic_mmio_gpio.h>
+
+#define MMIO_74XX_DIR_IN	(0 << 8)
+#define MMIO_74XX_DIR_OUT	(1 << 8)
+#define MMIO_74XX_BIT_CNT(x)	((x) & 0xff)
+
+struct mmio_74xx_gpio_priv {
+	struct bgpio_chip	bgc;
+	unsigned int		flags;
+};
+
+static const struct of_device_id mmio_74xx_gpio_ids[] = {
+	{
+		.compatible	= "ti,741g125",
+		.data		= (const void *)(MMIO_74XX_DIR_IN | 1),
+	},
+	{
+		.compatible	= "ti,742g125",
+		.data		= (const void *)(MMIO_74XX_DIR_IN | 2),
+	},
+	{
+		.compatible	= "ti,74125",
+		.data		= (const void *)(MMIO_74XX_DIR_IN | 4),
+	},
+	{
+		.compatible	= "ti,74365",
+		.data		= (const void *)(MMIO_74XX_DIR_IN | 6),
+	},
+	{
+		.compatible	= "ti,74244",
+		.data		= (const void *)(MMIO_74XX_DIR_IN | 8),
+	},
+	{
+		.compatible	= "ti,741624",
+		.data		= (const void *)(MMIO_74XX_DIR_IN | 16),
+	},
+	{
+		.compatible	= "ti,741g74",
+		.data		= (const void *)(MMIO_74XX_DIR_OUT | 1),
+	},
+	{
+		.compatible	= "ti,7474",
+		.data		= (const void *)(MMIO_74XX_DIR_OUT | 2),
+	},
+	{
+		.compatible	= "ti,74175",
+		.data		= (const void *)(MMIO_74XX_DIR_OUT | 4),
+	},
+	{
+		.compatible	= "ti,74174",
+		.data		= (const void *)(MMIO_74XX_DIR_OUT | 6),
+	},
+	{
+		.compatible	= "ti,74273",
+		.data		= (const void *)(MMIO_74XX_DIR_OUT | 8),
+	},
+	{
+		.compatible	= "ti,7416374",
+		.data		= (const void *)(MMIO_74XX_DIR_OUT | 16),
+	},
+	{ }
+};
+
+static inline
+struct mmio_74xx_gpio_priv *to_mmio_74xx_gpio_priv(struct gpio_chip *gc)
+{
+	struct bgpio_chip *bgc =
+		container_of(gc, struct bgpio_chip, gc);
+
+	return container_of(bgc, struct mmio_74xx_gpio_priv, bgc);
+}
+
+static int mmio_74xx_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+	struct mmio_74xx_gpio_priv *priv = to_mmio_74xx_gpio_priv(gc);
+
+	if (priv->flags & MMIO_74XX_DIR_OUT)
+		return GPIOF_DIR_OUT;
+
+	return GPIOF_DIR_IN;
+}
+
+static int mmio_74xx_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+	struct mmio_74xx_gpio_priv *priv = to_mmio_74xx_gpio_priv(gc);
+
+	return (priv->flags & MMIO_74XX_DIR_OUT) ? -ENOTSUPP : 0;
+}
+
+static int mmio_74xx_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+	struct mmio_74xx_gpio_priv *priv = to_mmio_74xx_gpio_priv(gc);
+
+	if (priv->flags & MMIO_74XX_DIR_OUT) {
+		gc->ops->set(gc, gpio, val);
+		return 0;
+	}
+
+	return -ENOTSUPP;
+}
+
+static int mmio_74xx_gpio_probe(struct device_d *dev)
+{
+	struct mmio_74xx_gpio_priv *priv;
+	void __iomem *dat;
+	int err;
+	struct gpio_chip *gc;
+
+	priv = xzalloc(sizeof(*priv));
+
+	priv->flags = (uintptr_t)of_device_get_match_data(dev);
+
+	dat = dev_request_mem_region(dev, 0);
+	if (IS_ERR(dat))
+		return PTR_ERR(dat);
+
+	err = bgpio_init(&priv->bgc, dev,
+			 DIV_ROUND_UP(MMIO_74XX_BIT_CNT(priv->flags), 8),
+			 dat, NULL, NULL, NULL, NULL, 0);
+	if (err)
+		return err;
+
+	gc = &priv->bgc.gc;
+	gc->ops->direction_input = mmio_74xx_dir_in;
+	gc->ops->direction_output = mmio_74xx_dir_out;
+	gc->ops->get_direction = mmio_74xx_get_direction;
+	gc->ngpio = MMIO_74XX_BIT_CNT(priv->flags);
+
+	dev->priv = priv;
+
+	return gpiochip_add(gc);
+}
+
+static struct driver_d mmio_74xx_gpio_driver = {
+	.name = "74xx-mmio-gpio",
+	.of_compatible	= DRV_OF_COMPAT(mmio_74xx_gpio_ids),
+	.probe = mmio_74xx_gpio_probe,
+};
+
+coredevice_platform_driver(mmio_74xx_gpio_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
+MODULE_DESCRIPTION("74xx MMIO GPIO driver");
-- 
2.31.1


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 07/10] spi: add litex spiflash driver
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
                   ` (5 preceding siblings ...)
  2021-05-25  7:19 ` [PATCH v3 06/10] gpio: add driver for 74xx-ICs with MMIO access Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 08/10] net: add LiteEth driver Antony Pavlov
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 drivers/spi/Kconfig          |   3 +
 drivers/spi/Makefile         |   1 +
 drivers/spi/litex_spiflash.c | 241 +++++++++++++++++++++++++++++++++++
 3 files changed, 245 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 323d93efeb..714d30e909 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -74,6 +74,9 @@ config DRIVER_SPI_IMX_2_3
 	depends on ARCH_IMX50 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6 || ARCH_IMX7 || ARCH_IMX8MQ
 	default y
 
+config DRIVER_SPI_LITEX_SPIFLASH
+	bool "Litex SPIFLASH bitbang master driver"
+
 config DRIVER_SPI_MXS
 	bool "i.MX (23,28) SPI Master driver"
 	depends on ARCH_IMX28
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 908d514a01..ac95ffc1db 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_DRIVER_SPI_ATH79) += ath79_spi.o
 obj-$(CONFIG_DRIVER_SPI_GPIO) += gpio_spi.o
 obj-$(CONFIG_DRIVER_SPI_FSL_QUADSPI) += spi-fsl-qspi.o
 obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o
+obj-$(CONFIG_DRIVER_SPI_LITEX_SPIFLASH) += litex_spiflash.o
 obj-$(CONFIG_DRIVER_SPI_MVEBU) += mvebu_spi.o
 obj-$(CONFIG_DRIVER_SPI_MXS) += mxs_spi.o
 obj-$(CONFIG_DRIVER_SPI_ALTERA) += altera_spi.o
diff --git a/drivers/spi/litex_spiflash.c b/drivers/spi/litex_spiflash.c
new file mode 100644
index 0000000000..26ef207699
--- /dev/null
+++ b/drivers/spi/litex_spiflash.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <spi/spi.h>
+#include <io.h>
+
+struct litex_spiflash_spi {
+	struct spi_master	master;
+	void __iomem		*regs;
+	u32			val;
+};
+
+#define SPIFLASH_BITBANG 0x0
+#define  SPIFLASH_BB_MOSI BIT(0)
+#define  SPIFLASH_BB_CLK BIT(1)
+#define  SPIFLASH_BB_CSN BIT(2)
+#define  SPIFLASH_BB_DIR BIT(3)
+
+#define SPIFLASH_MISO 0x4
+#define SPIFLASH_BITBANG_EN 0x8
+
+static inline u32 litex_spiflash_spi_rr(struct litex_spiflash_spi *sp, int reg)
+{
+	return readl(sp->regs + reg);
+}
+
+static inline void litex_spiflash_spi_wr(struct litex_spiflash_spi *sp, u32 val, int reg)
+{
+	writel(val, sp->regs + reg);
+}
+
+static inline void setbits(struct litex_spiflash_spi *sp, int bits, int on)
+{
+	/*
+	 * We are the only user of SCSPTR so no locking is required.
+	 * Reading bit 2 and 0 in SCSPTR gives pin state as input.
+	 * Writing the same bits sets the output value.
+	 * This makes regular read-modify-write difficult so we
+	 * use sp->val to keep track of the latest register value.
+	 */
+
+	if (on)
+		sp->val |= bits;
+	else
+		sp->val &= ~bits;
+
+	litex_spiflash_spi_wr(sp, sp->val, SPIFLASH_BITBANG);
+}
+
+static inline struct litex_spiflash_spi *litex_spiflash_spidev_to_sp(struct spi_device *spi)
+{
+	return container_of(spi->master, struct litex_spiflash_spi, master);
+}
+
+static inline void setsck(struct spi_device *spi, int on)
+{
+	struct litex_spiflash_spi *sc = litex_spiflash_spidev_to_sp(spi);
+
+	setbits(sc, SPIFLASH_BB_CLK, on);
+}
+
+static inline void setmosi(struct spi_device *spi, int on)
+{
+	struct litex_spiflash_spi *sc = litex_spiflash_spidev_to_sp(spi);
+
+	sc->val &= ~SPIFLASH_BB_DIR;
+	setbits(sc, SPIFLASH_BB_MOSI, on);
+}
+
+static inline u32 getmiso(struct spi_device *spi)
+{
+	struct litex_spiflash_spi *sc = litex_spiflash_spidev_to_sp(spi);
+
+	setbits(sc, SPIFLASH_BB_DIR, 1);
+	return !!((litex_spiflash_spi_rr(sc, SPIFLASH_MISO) & 1));
+}
+
+#define spidelay(nsecs) udelay(nsecs/1000)
+
+#include "spi-bitbang-txrx.h"
+
+static inline void litex_spiflash_spi_chipselect(struct litex_spiflash_spi *sc, int on)
+{
+	setbits(sc, SPIFLASH_BB_CSN, on);
+}
+
+static int litex_spiflash_spi_setup(struct spi_device *spi)
+{
+	struct spi_master *master = spi->master;
+	struct device_d spi_dev = spi->dev;
+
+	if (spi->bits_per_word != 8) {
+		dev_err(master->dev, "master doesn't support %d bits per word requested by %s\n",
+			spi->bits_per_word, spi_dev.name);
+		return -EINVAL;
+	}
+
+	if ((spi->mode & (SPI_CPHA | SPI_CPOL)) != SPI_MODE_0) {
+		dev_err(master->dev, "master doesn't support SPI_MODE%d requested by %s\n",
+			spi->mode & (SPI_CPHA | SPI_CPOL), spi_dev.name);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int litex_spiflash_spi_read(struct spi_device *spi, void *buf, size_t nbyte)
+{
+	ssize_t cnt = 0;
+	u8 *rxf_buf = buf;
+
+	while (cnt < nbyte) {
+		*rxf_buf = bitbang_txrx_be_cpha1(spi, 1000, 1, 0, 8);
+		rxf_buf++;
+		cnt++;
+	}
+
+	return cnt;
+}
+
+static int litex_spiflash_spi_write(struct spi_device *spi,
+				const void *buf, size_t nbyte)
+{
+	ssize_t cnt = 0;
+	const u8 *txf_buf = buf;
+
+	while (cnt < nbyte) {
+		bitbang_txrx_be_cpha1(spi, 1000, 1, (u32)*txf_buf, 8);
+		txf_buf++;
+		cnt++;
+	}
+
+	return 0;
+}
+
+static int litex_spiflash_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
+{
+	struct litex_spiflash_spi *sc = litex_spiflash_spidev_to_sp(spi);
+	struct spi_transfer *t;
+
+	mesg->actual_length = 0;
+
+	/* activate chip select signal */
+	litex_spiflash_spi_chipselect(sc, 0);
+
+	list_for_each_entry(t, &mesg->transfers, transfer_list) {
+
+		if (t->tx_buf)
+			litex_spiflash_spi_write(spi, t->tx_buf, t->len);
+
+		if (t->rx_buf)
+			litex_spiflash_spi_read(spi, t->rx_buf, t->len);
+
+		mesg->actual_length += t->len;
+	}
+
+	/* inactivate chip select signal */
+	litex_spiflash_spi_chipselect(sc, 1);
+
+	return 0;
+}
+
+static void litex_spiflash_spi_enable(struct litex_spiflash_spi *sp)
+{
+	u32 val;
+
+	/* set SPIFLASH_BB_DIR = 0 */
+	val = SPIFLASH_BB_CSN | SPIFLASH_BB_CLK | SPIFLASH_BB_MOSI;
+	litex_spiflash_spi_wr(sp, val, SPIFLASH_BITBANG);
+
+	/* enable GPIO mode */
+	litex_spiflash_spi_wr(sp, 1, SPIFLASH_BITBANG_EN);
+}
+
+static void litex_spiflash_spi_disable(struct litex_spiflash_spi *sp)
+{
+	/* disable GPIO mode */
+	litex_spiflash_spi_wr(sp, 0, SPIFLASH_BITBANG_EN);
+}
+
+static int litex_spiflash_spi_probe(struct device_d *dev)
+{
+	struct resource *iores;
+	struct spi_master *master;
+	struct litex_spiflash_spi *litex_spiflash_spi;
+
+	litex_spiflash_spi = xzalloc(sizeof(*litex_spiflash_spi));
+	dev->priv = litex_spiflash_spi;
+
+	master = &litex_spiflash_spi->master;
+	master->dev = dev;
+
+	master->bus_num = dev->id;
+	master->setup = litex_spiflash_spi_setup;
+	master->transfer = litex_spiflash_spi_transfer;
+	master->num_chipselect = 1;
+
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
+	litex_spiflash_spi->regs = IOMEM(iores->start);
+
+	litex_spiflash_spi_enable(litex_spiflash_spi);
+
+	/* inactivate chip select signal */
+	litex_spiflash_spi_chipselect(litex_spiflash_spi, 1);
+
+	spi_register_master(master);
+
+	return 0;
+}
+
+static void litex_spiflash_spi_remove(struct device_d *dev)
+{
+	struct litex_spiflash_spi *sp = dev->priv;
+
+	litex_spiflash_spi_disable(sp);
+}
+
+static __maybe_unused struct of_device_id litex_spiflash_spi_dt_ids[] = {
+	{
+		.compatible = "litex,spiflash",
+	},
+	{
+		/* sentinel */
+	}
+};
+
+static struct driver_d litex_spiflash_spi_driver = {
+	.name  = "litex-spiflash",
+	.probe = litex_spiflash_spi_probe,
+	.remove = litex_spiflash_spi_remove,
+	.of_compatible = DRV_OF_COMPAT(litex_spiflash_spi_dt_ids),
+};
+device_platform_driver(litex_spiflash_spi_driver);
-- 
2.31.1


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 08/10] net: add LiteEth driver
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
                   ` (6 preceding siblings ...)
  2021-05-25  7:19 ` [PATCH v3 07/10] spi: add litex spiflash driver Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-05-25  7:19 ` [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support Antony Pavlov
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Marek Czerski, Ahmad Fatoum

LiteEth provides a small footprint and configurable Ethernet core.

LiteEth is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

Using Migen to describe the HDL allows the core to be highly and easily configurable.

LiteEth can be used as LiteX library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.

See https://github.com/enjoy-digital/liteeth for details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Marek Czerski <m.czerski@ap-tech.pl>
---
 drivers/net/Kconfig   |   8 +
 drivers/net/Makefile  |   1 +
 drivers/net/liteeth.c | 376 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 385 insertions(+)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 0d55ea7a3b..4818f52603 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -271,6 +271,14 @@ config TSE_USE_DEDICATED_DESC_MEM
 	  reserved with a malloc but directly mapped to the memory
 	  address (defined in config.h)
 
+config DRIVER_NET_LITEETH
+	bool "LiteX ethernet driver"
+	select PHYLIB
+	select MDIO_BITBANG
+	help
+	  This option enables support for the LiteX LiteEth
+	  ethernet IP core.
+
 source "drivers/net/phy/Kconfig"
 source "drivers/net/usb/Kconfig"
 
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 656d45a868..bb751943f6 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -36,3 +36,4 @@ obj-$(CONFIG_DRIVER_NET_TAP)		+= tap.o
 obj-$(CONFIG_DRIVER_NET_TSE)		+= altera_tse.o
 obj-$(CONFIG_DRIVER_NET_EFI_SNP)	+= efi-snp.o
 obj-$(CONFIG_DRIVER_NET_AG71XX)		+= ag71xx.o
+obj-$(CONFIG_DRIVER_NET_LITEETH)	+= liteeth.o
diff --git a/drivers/net/liteeth.c b/drivers/net/liteeth.c
new file mode 100644
index 0000000000..137cb854c5
--- /dev/null
+++ b/drivers/net/liteeth.c
@@ -0,0 +1,376 @@
+/*
+ * LiteX Liteeth Ethernet
+ *
+ * Copyright 2017 Joel Stanley <joel@jms.id.au>
+ *
+ * Ported to barebox from linux kernel
+ *   Copyright (C) 2019-2021 Antony Pavlov <antonynpavlov@gmail.com>
+ *   Copyright (C) 2021 Marek Czerski <m.czerski@ap-tech.pl>
+ *
+ */
+
+#include <common.h>
+#include <io.h>
+#include <linux/iopoll.h>
+#include <malloc.h>
+#include <net.h>
+#include <init.h>
+#include <of_net.h>
+#include <linux/phy.h>
+#include <linux/mdio-bitbang.h>
+
+#define DRV_NAME	"liteeth"
+
+#define LITEETH_WRITER_SLOT		0x00
+#define LITEETH_WRITER_LENGTH		0x04
+#define LITEETH_WRITER_ERRORS		0x08
+#define LITEETH_WRITER_EV_STATUS	0x0c
+#define LITEETH_WRITER_EV_PENDING	0x10
+#define LITEETH_WRITER_EV_ENABLE	0x14
+#define LITEETH_READER_START		0x18
+#define LITEETH_READER_READY		0x1c
+#define LITEETH_READER_LEVEL		0x20
+#define LITEETH_READER_SLOT		0x24
+#define LITEETH_READER_LENGTH		0x28
+#define LITEETH_READER_EV_STATUS	0x2c
+#define LITEETH_READER_EV_PENDING	0x30
+#define LITEETH_READER_EV_ENABLE	0x34
+#define LITEETH_PREAMBLE_CRC		0x38
+#define LITEETH_PREAMBLE_ERRORS		0x3c
+#define LITEETH_CRC_ERRORS		0x40
+
+#define LITEETH_PHY_CRG_RESET		0x00
+#define LITEETH_MDIO_W			0x04
+#define  MDIO_W_CLK			BIT(0)
+#define  MDIO_W_OE			BIT(1)
+#define  MDIO_W_DO			BIT(2)
+
+#define LITEETH_MDIO_R			0x08
+#define  MDIO_R_DI			BIT(0)
+
+#define LITEETH_BUFFER_SIZE		0x800
+#define MAX_PKT_SIZE			LITEETH_BUFFER_SIZE
+
+struct liteeth {
+	struct device_d *dev;
+	struct eth_device edev;
+	void __iomem *base;
+	void __iomem *mdio_base;
+	struct mii_bus *mii_bus;
+	struct mdiobb_ctrl mdiobb;
+
+	/* Link management */
+	int cur_duplex;
+	int cur_speed;
+
+	/* Tx */
+	int tx_slot;
+	int num_tx_slots;
+	void __iomem *tx_base;
+
+	/* Rx */
+	int rx_slot;
+	int num_rx_slots;
+	void __iomem *rx_base;
+};
+
+static inline void litex_write8(void __iomem *addr, u8 val)
+{
+	writeb(val, addr);
+}
+
+static inline void litex_write16(void __iomem *addr, u16 val)
+{
+	writew(val, addr);
+}
+
+static inline u8 litex_read8(void __iomem *addr)
+{
+	return readb(addr);
+}
+
+static inline u32 litex_read32(void __iomem *addr)
+{
+	return readl(addr);
+}
+
+static void liteeth_mdio_w_modify(struct liteeth *priv, u8 clear, u8 set)
+{
+	void __iomem *mdio_w = priv->mdio_base + LITEETH_MDIO_W;
+
+	litex_write8(mdio_w, (litex_read8(mdio_w) & ~clear) | set);
+}
+
+static void liteeth_mdio_ctrl(struct mdiobb_ctrl *ctrl, u8 mask, int set)
+{
+	struct liteeth *priv = container_of(ctrl, struct liteeth, mdiobb);
+
+	liteeth_mdio_w_modify(priv, mask, set ? mask : 0);
+}
+
+/* MDC pin control */
+static void liteeth_set_mdc(struct mdiobb_ctrl *ctrl, int level)
+{
+	liteeth_mdio_ctrl(ctrl, MDIO_W_CLK, level);
+}
+
+/* Data I/O pin control */
+static void liteeth_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
+{
+	liteeth_mdio_ctrl(ctrl, MDIO_W_OE, output);
+}
+
+/* Set data bit */
+static void liteeth_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
+{
+	liteeth_mdio_ctrl(ctrl, MDIO_W_DO, value);
+}
+
+/* Get data bit */
+static int liteeth_get_mdio_data(struct mdiobb_ctrl *ctrl)
+{
+	struct liteeth *priv = container_of(ctrl, struct liteeth, mdiobb);
+
+	return (litex_read8(priv->mdio_base + LITEETH_MDIO_R) & MDIO_R_DI) != 0;
+}
+
+/* MDIO bus control struct */
+static struct mdiobb_ops bb_ops = {
+	.set_mdc = liteeth_set_mdc,
+	.set_mdio_dir = liteeth_set_mdio_dir,
+	.set_mdio_data = liteeth_set_mdio_data,
+	.get_mdio_data = liteeth_get_mdio_data,
+};
+
+static int liteeth_init_dev(struct eth_device *edev)
+{
+	return 0;
+}
+
+static int liteeth_eth_open(struct eth_device *edev)
+{
+	struct liteeth *priv = edev->priv;
+	int ret;
+
+	/* Disable events */
+	litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0);
+	litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0);
+
+	/* Clear pending events? */
+	litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);
+	litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1);
+
+	ret = phy_device_connect(edev, priv->mii_bus, -1, NULL, 0, -1);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int liteeth_eth_send(struct eth_device *edev, void *packet,
+				int packet_length)
+{
+	struct liteeth *priv = edev->priv;
+	void *txbuffer;
+	int ret;
+	u8 val;
+	u8 reg;
+
+	reg = litex_read8(priv->base + LITEETH_READER_EV_PENDING);
+	if (reg) {
+		litex_write8(priv->base + LITEETH_READER_EV_PENDING, reg);
+	}
+
+	/* Reject oversize packets */
+	if (unlikely(packet_length > MAX_PKT_SIZE)) {
+		dev_err(priv->dev, "tx packet too big\n");
+		goto drop;
+	}
+
+	txbuffer = priv->tx_base + priv->tx_slot * LITEETH_BUFFER_SIZE;
+	memcpy(txbuffer, packet, packet_length);
+	litex_write8(priv->base + LITEETH_READER_SLOT, priv->tx_slot);
+	litex_write16(priv->base + LITEETH_READER_LENGTH, packet_length);
+
+	ret = readb_poll_timeout(priv->base + LITEETH_READER_READY,
+			val, val, 1000);
+	if (ret == -ETIMEDOUT) {
+		dev_err(priv->dev, "LITEETH_READER_READY timed out\n");
+		goto drop;
+	}
+
+	litex_write8(priv->base + LITEETH_READER_START, 1);
+
+	priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;
+
+drop:
+	return 0;
+}
+
+static int liteeth_eth_rx(struct eth_device *edev)
+{
+	struct liteeth *priv = edev->priv;
+	u8 rx_slot;
+	int len = 0;
+	u8 reg;
+
+	reg = litex_read8(priv->base + LITEETH_WRITER_EV_PENDING);
+	if (!reg) {
+		goto done;
+	}
+
+	len = litex_read32(priv->base + LITEETH_WRITER_LENGTH);
+	if (len == 0 || len > 2048) {
+		len = 0;
+		dev_err(priv->dev, "%s: invalid len %d\n", __func__, len);
+		litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, reg);
+		goto done;
+	}
+
+	rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT);
+
+	memcpy(NetRxPackets[0], priv->rx_base + rx_slot * LITEETH_BUFFER_SIZE, len);
+
+	net_receive(edev, NetRxPackets[0], len);
+
+	litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, reg);
+
+done:
+	return len;
+}
+
+static void liteeth_eth_halt(struct eth_device *edev)
+{
+	struct liteeth *priv = edev->priv;
+
+	litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0);
+	litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0);
+}
+
+static void liteeth_reset_hw(struct liteeth *priv)
+{
+	/* Reset, twice */
+	litex_write8(priv->base + LITEETH_PHY_CRG_RESET, 0);
+	udelay(10);
+	litex_write8(priv->base + LITEETH_PHY_CRG_RESET, 1);
+	udelay(10);
+	litex_write8(priv->base + LITEETH_PHY_CRG_RESET, 0);
+	udelay(10);
+}
+
+static int liteeth_get_ethaddr(struct eth_device *edev, unsigned char *m)
+{
+	return 0;
+}
+
+static int liteeth_set_ethaddr(struct eth_device *edev,
+					const unsigned char *mac_addr)
+{
+	return 0;
+}
+
+static int liteeth_probe(struct device_d *dev)
+{
+	struct device_node *np = dev->device_node;
+	struct eth_device *edev;
+	void __iomem *buf_base;
+	struct liteeth *priv;
+	int err;
+
+	priv = xzalloc(sizeof(struct liteeth));
+	edev = &priv->edev;
+	edev->priv = priv;
+	priv->dev = dev;
+
+	priv->base = dev_request_mem_region(dev, 0);
+	if (IS_ERR(priv->base)) {
+		err = PTR_ERR(priv->base);
+		goto err;
+	}
+
+	priv->mdio_base = dev_request_mem_region(dev, 1);
+	if (IS_ERR(priv->mdio_base)) {
+		err = PTR_ERR(priv->mdio_base);
+		goto err;
+	}
+
+	buf_base = dev_request_mem_region(dev, 2);
+	if (IS_ERR(buf_base)) {
+		err = PTR_ERR(buf_base);
+		goto err;
+	}
+
+	err = of_property_read_u32(np, "rx-fifo-depth",
+			&priv->num_rx_slots);
+	if (err) {
+		dev_err(dev, "unable to get rx-fifo-depth\n");
+		goto err;
+	}
+
+	err = of_property_read_u32(np, "tx-fifo-depth",
+			&priv->num_tx_slots);
+	if (err) {
+		dev_err(dev, "unable to get tx-fifo-depth\n");
+		goto err;
+	}
+
+	/* Rx slots */
+	priv->rx_base = buf_base;
+	priv->rx_slot = 0;
+
+	/* Tx slots come after Rx slots */
+	priv->tx_base = buf_base + priv->num_rx_slots * LITEETH_BUFFER_SIZE;
+	priv->tx_slot = 0;
+
+	edev->init = liteeth_init_dev;
+	edev->open = liteeth_eth_open;
+	edev->send = liteeth_eth_send;
+	edev->recv = liteeth_eth_rx;
+	edev->get_ethaddr = liteeth_get_ethaddr;
+	edev->set_ethaddr = liteeth_set_ethaddr;
+	edev->halt = liteeth_eth_halt;
+	edev->parent = dev;
+
+	priv->mdiobb.ops = &bb_ops;
+
+	priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
+	priv->mii_bus->parent = dev;
+
+	liteeth_reset_hw(priv);
+
+	err = eth_register(edev);
+	if (err) {
+		dev_err(dev, "failed to register edev\n");
+		goto err;
+	}
+
+	err = mdiobus_register(priv->mii_bus);
+	if (err) {
+		dev_err(dev, "failed to register mii_bus\n");
+		goto err;
+	}
+
+	dev_info(dev, DRV_NAME " driver registered\n");
+
+	return 0;
+
+err:
+	return err;
+}
+
+static const struct of_device_id liteeth_dt_ids[] = {
+	{
+		.compatible = "litex,liteeth"
+	}, {
+	}
+};
+
+static struct driver_d liteeth_driver = {
+	.name = DRV_NAME,
+	.probe = liteeth_probe,
+	.of_compatible = DRV_OF_COMPAT(liteeth_dt_ids),
+};
+device_platform_driver(liteeth_driver);
+
+MODULE_AUTHOR("Joel Stanley <joel@jms.id.au>");
+MODULE_LICENSE("GPL");
-- 
2.31.1


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barebox@lists.infradead.org
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
                   ` (7 preceding siblings ...)
  2021-05-25  7:19 ` [PATCH v3 08/10] net: add LiteEth driver Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-05-25  7:47   ` Jan Lübbe
  2021-05-25  7:19 ` [PATCH v3 10/10] RISC-V: add litex_linux_defconfig Antony Pavlov
  2021-08-11  8:52 ` [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Ahmad Fatoum
  10 siblings, 1 reply; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

LiteX is a Migen-based System on Chip, supporting softcore
VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.

See https://github.com/enjoy-digital/litex and
https://github.com/litex-hub/linux-on-litex-vexriscv
for details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/riscv/Kconfig.socs                  |  14 +++
 arch/riscv/boards/Makefile               |   1 +
 arch/riscv/boards/litex-linux/Makefile   |   3 +
 arch/riscv/boards/litex-linux/lowlevel.c |  22 ++++
 arch/riscv/dts/Makefile                  |   1 +
 arch/riscv/dts/litex-linux.dts           |  92 +++++++++++++++++
 arch/riscv/dts/litex_soc_linux.dtsi      |  49 +++++++++
 arch/riscv/include/asm/debug_ll.h        |   3 +
 arch/riscv/include/asm/debug_ll_litex.h  | 123 +++++++++++++++++++++++
 common/Kconfig                           |   4 +
 images/Makefile.riscv                    |   4 +
 11 files changed, 316 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 67d19caeb3..3ae66776f0 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -42,4 +42,18 @@ config BOARD_HIFIVE
 
 endif
 
+config SOC_LITEX
+	bool "LiteX SoCs"
+	depends on ARCH_RV32I
+	select HAS_ASM_DEBUG_LL
+	select HAS_NMON
+	select USE_COMPRESSED_DTB
+	select RISCV_TIMER
+
+config BOARD_LITEX_LINUX
+	bool "litex linux board"
+	depends on SOC_LITEX
+	select RISCV_M_MODE
+	def_bool y
+
 endmenu
diff --git a/arch/riscv/boards/Makefile b/arch/riscv/boards/Makefile
index 99f22f32b4..0468871fde 100644
--- a/arch/riscv/boards/Makefile
+++ b/arch/riscv/boards/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_BOARD_ERIZO_GENERIC)	+= erizo/
 obj-$(CONFIG_BOARD_HIFIVE)		+= hifive/
+obj-$(CONFIG_BOARD_LITEX_LINUX)		+= litex-linux/
diff --git a/arch/riscv/boards/litex-linux/Makefile b/arch/riscv/boards/litex-linux/Makefile
new file mode 100644
index 0000000000..3d217ffe0b
--- /dev/null
+++ b/arch/riscv/boards/litex-linux/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+pbl-y += lowlevel.o
diff --git a/arch/riscv/boards/litex-linux/lowlevel.c b/arch/riscv/boards/litex-linux/lowlevel.c
new file mode 100644
index 0000000000..da23ef5633
--- /dev/null
+++ b/arch/riscv/boards/litex-linux/lowlevel.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <asm/barebox-riscv.h>
+#include <debug_ll.h>
+#include <asm/riscv_nmon.h>
+
+ENTRY_FUNCTION(start_litex_linux, a0, a1, a2)
+{
+	extern char __dtb_z_litex_linux_start[];
+	void *fdt;
+
+	barebox_nmon_entry();
+
+	putc_ll('>');
+
+	/* On POR, we are running from read-only memory here. */
+
+	fdt = __dtb_z_litex_linux_start + get_runtime_offset();
+
+	barebox_riscv_machine_entry(0x40000000, SZ_256M, fdt);
+}
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 17fdc9445b..683038189f 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,5 +7,6 @@ obj- += dummy.o
 pbl-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o
 pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \
                               hifive-unleashed-a00.dtb.o
+pbl-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux.dtb.o
 
 clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
diff --git a/arch/riscv/dts/litex-linux.dts b/arch/riscv/dts/litex-linux.dts
new file mode 100644
index 0000000000..d21fa57e30
--- /dev/null
+++ b/arch/riscv/dts/litex-linux.dts
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "litex_soc_linux.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "LiteX VexRiscV-SoC-Linux";
+	compatible = "litex,vexriscv-soc-linux";
+
+	aliases {
+		rom = &rom;
+		sram = &sram;
+	};
+
+	/* ARTY board */
+	rom: rom@00000000 {
+		compatible = "mmio-sram";
+		reg = <0x00000000 0x00008000>;
+		read-only;
+	};
+
+	sram: sram@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 0x00004000>;
+	};
+
+	main_ram: memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&mac0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
+
+/ {
+	ledsgpio: gpio@f000a800 {
+		compatible = "ti,74175";
+		reg = <0xf000a800 0x4>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		ld0 {
+			label = "arty:green:ld0";
+			gpios = <&ledsgpio 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		ld1 {
+			label = "arty:green:ld1";
+			gpios = <&ledsgpio 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		ld2 {
+			label = "arty:green:ld2";
+			gpios = <&ledsgpio 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		ld3 {
+			label = "arty:green:ld3";
+			gpios = <&ledsgpio 3 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	swgpio: gpio@f0006000 {
+		compatible = "ti,74125";
+		reg = <0xf0006000 0x4>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
diff --git a/arch/riscv/dts/litex_soc_linux.dtsi b/arch/riscv/dts/litex_soc_linux.dtsi
new file mode 100644
index 0000000000..32382b8dc2
--- /dev/null
+++ b/arch/riscv/dts/litex_soc_linux.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+/ {
+	compatible = "litex,vexriscv-soc-linux";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		timebase-frequency = <100000000>; // 100 MHz
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "spinalhdl,vexriscv", "riscv";
+			reg = <0>;
+		};
+	};
+
+	uart0: serial@f0001000 {
+		compatible = "litex,uart";
+		reg = <0xf0001000 0x18>;
+		status = "disabled";
+	};
+
+	mac0: mac@f0009000 {
+		compatible = "litex,liteeth";
+		reg = <0xf0009000 0x7c /* base */
+			0xf0009800 0x0a /* mdio_base */
+			0xb0000000 0x2000>; /* buf_base */
+		tx-fifo-depth = <2>;
+		rx-fifo-depth = <2>;
+		status = "disabled";
+	};
+
+	spi0: spi@f000b800 {
+		compatible = "litex,spiflash";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg = <0xf000b800 0x100>;
+		status = "disabled";
+	};
+};
diff --git a/arch/riscv/include/asm/debug_ll.h b/arch/riscv/include/asm/debug_ll.h
index 6904460af9..050a1412d1 100644
--- a/arch/riscv/include/asm/debug_ll.h
+++ b/arch/riscv/include/asm/debug_ll.h
@@ -37,6 +37,9 @@ static inline void PUTC_LL(char ch)
 
 	writel(ch, uart0);
 }
+#elif defined CONFIG_DEBUG_LITEX
+
+#include <asm/debug_ll_litex.h>
 
 #endif
 
diff --git a/arch/riscv/include/asm/debug_ll_litex.h b/arch/riscv/include/asm/debug_ll_litex.h
new file mode 100644
index 0000000000..2fcdd9b0ec
--- /dev/null
+++ b/arch/riscv/include/asm/debug_ll_litex.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2019 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_DEBUG_LL_LITEX__
+#define __ASM_DEBUG_LL_LITEX__
+
+/** @file
+ *  This File contains declaration for early output support
+ */
+
+#include <linux/kconfig.h>
+
+#define DEBUG_LL_UART_ADDR	0xf0001000
+#define UART_RXTX	0x00
+#define UART_TXFULL	0x04
+#define UART_RXEMPTY	0x08
+#define UART_EV_PENDING	0x10
+#define  UART_EV_RX	(1 << 1)
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * C macros
+ */
+
+#include <asm/io.h>
+
+static inline void PUTC_LL(char ch)
+{
+#ifdef CONFIG_DEBUG_LL
+	/* wait for space */
+	while (__raw_readb((u8 *)DEBUG_LL_UART_ADDR + UART_TXFULL))
+		;
+
+	__raw_writeb(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_RXTX);
+#endif /* CONFIG_DEBUG_LL */
+}
+#else /* __ASSEMBLY__ */
+/*
+ * Macros for use in assembly language code
+ */
+
+/*
+ * output a character in a0
+ */
+.macro	debug_ll_outc_a0
+#ifdef CONFIG_DEBUG_LL
+
+	li	t0, DEBUG_LL_UART_ADDR
+
+201:
+	lbu	t1, UART_TXFULL(t0)	/* uart tx full ? */
+	andi	t1, t1, 0xff
+	bnez	t1, 201b		/* try again */
+
+	sb	a0, UART_RXTX(t0)	/* write the character */
+
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * output a character
+ */
+.macro	debug_ll_outc chr
+#ifdef CONFIG_DEBUG_LL
+	li	a0, \chr
+	debug_ll_outc_a0
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * check character in input buffer
+ * return value:
+ *  v0 = 0   no character in input buffer
+ *  v0 != 0  character in input buffer
+ */
+.macro	debug_ll_tstc
+#ifdef CONFIG_DEBUG_LL
+	li	t0, DEBUG_LL_UART_ADDR
+
+	/* get line status and check for data present */
+	lbu	s0, UART_RXEMPTY(t0)
+	bnez    s0, 243f
+	li	s0, 1
+	j	244f
+243:	li	s0, 0
+244:	nop
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * get character to v0
+ */
+.macro	debug_ll_getc
+#ifdef CONFIG_DEBUG_LL
+
+204:
+	debug_ll_tstc
+
+	/* try again */
+	beqz	s0, 204b
+
+	/* read a character */
+	lb	s0, UART_RXTX(t0)
+	li      t1, UART_EV_RX
+	sb	t1, UART_EV_PENDING(t0)
+
+#endif /* CONFIG_DEBUG_LL */
+.endm
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_DEBUG_LL_LITEX__ */
diff --git a/common/Kconfig b/common/Kconfig
index db7cc6713a..cd61b0ef6c 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1379,6 +1379,10 @@ config DEBUG_SIFIVE
 	bool "SiFive serial0 port"
 	depends on SOC_SIFIVE
 
+config DEBUG_LITEX
+	bool "LiteX serial port"
+	depends on SOC_LITEX
+
 endchoice
 
 config DEBUG_IMX_UART_PORT
diff --git a/images/Makefile.riscv b/images/Makefile.riscv
index c44c683431..24e33f5b11 100644
--- a/images/Makefile.riscv
+++ b/images/Makefile.riscv
@@ -15,3 +15,7 @@ pblb-$(CONFIG_BOARD_HIFIVE) += start_hifive_unmatched start_hifive_unleashed
 FILE_barebox-hifive-unmatched.img = start_hifive_unmatched.pblb
 FILE_barebox-hifive-unleashed.img = start_hifive_unleashed.pblb
 image-$(CONFIG_BOARD_HIFIVE) += barebox-hifive-unmatched.img barebox-hifive-unleashed.img
+
+pblb-$(CONFIG_BOARD_LITEX_LINUX) += start_litex_linux
+FILE_barebox-litex-linux.img = start_litex_linux.pblb
+image-$(CONFIG_BOARD_LITEX_LINUX) += barebox-litex-linux.img
-- 
2.31.1


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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 10/10] RISC-V: add litex_linux_defconfig
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
                   ` (8 preceding siblings ...)
  2021-05-25  7:19 ` [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support Antony Pavlov
@ 2021-05-25  7:19 ` Antony Pavlov
  2021-08-11  8:52 ` [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Ahmad Fatoum
  10 siblings, 0 replies; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/riscv/configs/litex_linux_defconfig | 76 ++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/arch/riscv/configs/litex_linux_defconfig b/arch/riscv/configs/litex_linux_defconfig
new file mode 100644
index 0000000000..c93a9cb57c
--- /dev/null
+++ b/arch/riscv/configs/litex_linux_defconfig
@@ -0,0 +1,76 @@
+CONFIG_SOC_LITEX=y
+CONFIG_STACK_SIZE=0x20000
+CONFIG_MALLOC_SIZE=0xf00000
+CONFIG_MALLOC_TLSF=y
+CONFIG_PANIC_HANG=y
+CONFIG_BAUDRATE=1000000
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_VERBOSE=y
+CONFIG_BOOTM_INITRD=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_BOOTM_OFTREE_UIMAGE=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEBUG_LL=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_CMP=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_OF_DUMP=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_NET=y
+CONFIG_NET_NFS=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_DRIVER_NET_LITEETH=y
+CONFIG_AR8327N_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_DP83867_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_NET_DSA_MV88E6XXX=y
+CONFIG_DRIVER_SPI_LITEX_SPIFLASH=y
+CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_MTD_M25P80=y
+CONFIG_CLOCKSOURCE_DUMMY_RATE=20000
+CONFIG_SRAM=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_GPIO_74XX_MMIO=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_PINCTRL is not set
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_DIGEST_CRC32_GENERIC=y
-- 
2.31.1


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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 05/10] litex serial: add setbrg callback
  2021-05-25  7:19 ` [PATCH v3 05/10] litex serial: add setbrg callback Antony Pavlov
@ 2021-05-25  7:36   ` Antony Pavlov
  2021-05-25 12:48     ` Ahmad Fatoum
  0 siblings, 1 reply; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  7:36 UTC (permalink / raw)
  To: Sascha Hauer, Ahmad Fatoum, Marek Czerski; +Cc: barebox

On Tue, 25 May 2021 10:19:47 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:

Hi all!


> From: Marek Czerski <m.czerski@ap-tech.pl>
> 
> setbrg callback (set baudrate) is needed by the loadx/loady commands.
> Because litex serial has fixed baudrate the callback only checks if
> the requested baudrate is the same as the CONFIG_BAUDRATE.
> ---
>  drivers/serial/serial_litex.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/serial/serial_litex.c b/drivers/serial/serial_litex.c
> index 8562a45ecc..9d35a6e44a 100644
> --- a/drivers/serial/serial_litex.c
> +++ b/drivers/serial/serial_litex.c
> @@ -58,6 +58,13 @@ static int litex_serial_tstc(struct console_device *cdev)
>  	return !litex_serial_readb(cdev, UART_RXEMPTY);
>  }
>  
> +static int litex_setial_setbaudrate(struct console_device *cdev, int baudrate)
> +{
> +	if (baudrate != CONFIG_BAUDRATE)
> +		return -EINVAL;
> +	return 0;
> +}
> +

I have sent this patch separately because it need special attention.

LiteX serial port hardware has fixed baudrate and setbaudrate has no sence.
On the other hand absent setnbaudrate() litex serial makes impossible 
to use Y-modem data trasfer.

I don't like CONFIG_BAUDRATE here. Can we use 

	if (baudrate != cdev->baudrate)
		return -EINVAL;
	return 0;

instead?

Please comment!

To: Ahmad
It looks like CONFIG_BAUDRATE is a one more global defconfig parameter
that complicates "one defconfig for all RISC-V boards" approach.

P.S. There is typo in litex_seTial_setbaudrate name. I have noted just now.
It should be fixed of cause.


>  static int litex_serial_probe(struct device_d *dev)
>  {
>  	struct resource *iores;
> @@ -73,7 +80,7 @@ static int litex_serial_probe(struct device_d *dev)
>  	cdev->tstc = &litex_serial_tstc;
>  	cdev->putc = &litex_serial_putc;
>  	cdev->getc = &litex_serial_getc;
> -	cdev->setbrg = NULL;
> +	cdev->setbrg = &litex_setial_setbaudrate;
>  
>  	console_register(cdev);
>  
> -- 
> 2.31.1
> 


-- 
Best regards,
  Antony Pavlov

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
  2021-05-25  7:19 ` [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support Antony Pavlov
@ 2021-05-25  7:47   ` Jan Lübbe
  2021-05-25  8:52     ` Antony Pavlov
  0 siblings, 1 reply; 19+ messages in thread
From: Jan Lübbe @ 2021-05-25  7:47 UTC (permalink / raw)
  To: Antony Pavlov, barebox; +Cc: Ahmad Fatoum

On Tue, 2021-05-25 at 10:19 +0300, Antony Pavlov wrote:
> LiteX is a Migen-based System on Chip, supporting softcore
> VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
> 
> See https://github.com/enjoy-digital/litex and
> https://github.com/litex-hub/linux-on-litex-vexriscv
> for details.

What are your steps for testing this? We have a few ECPIX-5 here, so we should
be able to reproduce this.

Regards,
Jan

> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> ---
>  arch/riscv/Kconfig.socs                  |  14 +++
>  arch/riscv/boards/Makefile               |   1 +
>  arch/riscv/boards/litex-linux/Makefile   |   3 +
>  arch/riscv/boards/litex-linux/lowlevel.c |  22 ++++
>  arch/riscv/dts/Makefile                  |   1 +
>  arch/riscv/dts/litex-linux.dts           |  92 +++++++++++++++++
>  arch/riscv/dts/litex_soc_linux.dtsi      |  49 +++++++++
>  arch/riscv/include/asm/debug_ll.h        |   3 +
>  arch/riscv/include/asm/debug_ll_litex.h  | 123 +++++++++++++++++++++++
>  common/Kconfig                           |   4 +
>  images/Makefile.riscv                    |   4 +
>  11 files changed, 316 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 67d19caeb3..3ae66776f0 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -42,4 +42,18 @@ config BOARD_HIFIVE
>  
> 
> 
> 
>  endif
>  
> 
> 
> 
> +config SOC_LITEX
> +	bool "LiteX SoCs"
> +	depends on ARCH_RV32I
> +	select HAS_ASM_DEBUG_LL
> +	select HAS_NMON
> +	select USE_COMPRESSED_DTB
> +	select RISCV_TIMER
> +
> +config BOARD_LITEX_LINUX
> +	bool "litex linux board"
> +	depends on SOC_LITEX
> +	select RISCV_M_MODE
> +	def_bool y
> +
>  endmenu
> diff --git a/arch/riscv/boards/Makefile b/arch/riscv/boards/Makefile
> index 99f22f32b4..0468871fde 100644
> --- a/arch/riscv/boards/Makefile
> +++ b/arch/riscv/boards/Makefile
> @@ -1,3 +1,4 @@
>  # SPDX-License-Identifier: GPL-2.0
>  obj-$(CONFIG_BOARD_ERIZO_GENERIC)	+= erizo/
>  obj-$(CONFIG_BOARD_HIFIVE)		+= hifive/
> +obj-$(CONFIG_BOARD_LITEX_LINUX)		+= litex-linux/
> diff --git a/arch/riscv/boards/litex-linux/Makefile b/arch/riscv/boards/litex-linux/Makefile
> new file mode 100644
> index 0000000000..3d217ffe0b
> --- /dev/null
> +++ b/arch/riscv/boards/litex-linux/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +pbl-y += lowlevel.o
> diff --git a/arch/riscv/boards/litex-linux/lowlevel.c b/arch/riscv/boards/litex-linux/lowlevel.c
> new file mode 100644
> index 0000000000..da23ef5633
> --- /dev/null
> +++ b/arch/riscv/boards/litex-linux/lowlevel.c
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include <common.h>
> +#include <asm/barebox-riscv.h>
> +#include <debug_ll.h>
> +#include <asm/riscv_nmon.h>
> +
> +ENTRY_FUNCTION(start_litex_linux, a0, a1, a2)
> +{
> +	extern char __dtb_z_litex_linux_start[];
> +	void *fdt;
> +
> +	barebox_nmon_entry();
> +
> +	putc_ll('>');
> +
> +	/* On POR, we are running from read-only memory here. */
> +
> +	fdt = __dtb_z_litex_linux_start + get_runtime_offset();
> +
> +	barebox_riscv_machine_entry(0x40000000, SZ_256M, fdt);
> +}
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index 17fdc9445b..683038189f 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -7,5 +7,6 @@ obj- += dummy.o
>  pbl-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o
>  pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \
>                                hifive-unleashed-a00.dtb.o
> +pbl-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux.dtb.o
>  
> 
> 
> 
>  clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
> diff --git a/arch/riscv/dts/litex-linux.dts b/arch/riscv/dts/litex-linux.dts
> new file mode 100644
> index 0000000000..d21fa57e30
> --- /dev/null
> +++ b/arch/riscv/dts/litex-linux.dts
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include "litex_soc_linux.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "LiteX VexRiscV-SoC-Linux";
> +	compatible = "litex,vexriscv-soc-linux";
> +
> +	aliases {
> +		rom = &rom;
> +		sram = &sram;
> +	};
> +
> +	/* ARTY board */
> +	rom: rom@00000000 {
> +		compatible = "mmio-sram";
> +		reg = <0x00000000 0x00008000>;
> +		read-only;
> +	};
> +
> +	sram: sram@20000000 {
> +		compatible = "mmio-sram";
> +		reg = <0x20000000 0x00004000>;
> +	};
> +
> +	main_ram: memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x40000000 0x10000000>;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&mac0 {
> +	status = "okay";
> +};
> +
> +&spi0 {
> +	status = "okay";
> +
> +	spiflash: w25q128@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "winbond,w25q128", "jedec,spi-nor";
> +		spi-max-frequency = <104000000>;
> +		reg = <0>;
> +	};
> +};
> +
> +/ {
> +	ledsgpio: gpio@f000a800 {
> +		compatible = "ti,74175";
> +		reg = <0xf000a800 0x4>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		ld0 {
> +			label = "arty:green:ld0";
> +			gpios = <&ledsgpio 0 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		ld1 {
> +			label = "arty:green:ld1";
> +			gpios = <&ledsgpio 1 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		ld2 {
> +			label = "arty:green:ld2";
> +			gpios = <&ledsgpio 2 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		ld3 {
> +			label = "arty:green:ld3";
> +			gpios = <&ledsgpio 3 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	swgpio: gpio@f0006000 {
> +		compatible = "ti,74125";
> +		reg = <0xf0006000 0x4>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +	};
> +};
> diff --git a/arch/riscv/dts/litex_soc_linux.dtsi b/arch/riscv/dts/litex_soc_linux.dtsi
> new file mode 100644
> index 0000000000..32382b8dc2
> --- /dev/null
> +++ b/arch/riscv/dts/litex_soc_linux.dtsi
> @@ -0,0 +1,49 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/dts-v1/;
> +
> +/ {
> +	compatible = "litex,vexriscv-soc-linux";
> +
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		timebase-frequency = <100000000>; // 100 MHz
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "spinalhdl,vexriscv", "riscv";
> +			reg = <0>;
> +		};
> +	};
> +
> +	uart0: serial@f0001000 {
> +		compatible = "litex,uart";
> +		reg = <0xf0001000 0x18>;
> +		status = "disabled";
> +	};
> +
> +	mac0: mac@f0009000 {
> +		compatible = "litex,liteeth";
> +		reg = <0xf0009000 0x7c /* base */
> +			0xf0009800 0x0a /* mdio_base */
> +			0xb0000000 0x2000>; /* buf_base */
> +		tx-fifo-depth = <2>;
> +		rx-fifo-depth = <2>;
> +		status = "disabled";
> +	};
> +
> +	spi0: spi@f000b800 {
> +		compatible = "litex,spiflash";
> +
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		reg = <0xf000b800 0x100>;
> +		status = "disabled";
> +	};
> +};
> diff --git a/arch/riscv/include/asm/debug_ll.h b/arch/riscv/include/asm/debug_ll.h
> index 6904460af9..050a1412d1 100644
> --- a/arch/riscv/include/asm/debug_ll.h
> +++ b/arch/riscv/include/asm/debug_ll.h
> @@ -37,6 +37,9 @@ static inline void PUTC_LL(char ch)
>  
> 
> 
> 
>  	writel(ch, uart0);
>  }
> +#elif defined CONFIG_DEBUG_LITEX
> +
> +#include <asm/debug_ll_litex.h>
>  
> 
> 
> 
>  #endif
>  
> 
> 
> 
> diff --git a/arch/riscv/include/asm/debug_ll_litex.h b/arch/riscv/include/asm/debug_ll_litex.h
> new file mode 100644
> index 0000000000..2fcdd9b0ec
> --- /dev/null
> +++ b/arch/riscv/include/asm/debug_ll_litex.h
> @@ -0,0 +1,123 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2019 Antony Pavlov <antonynpavlov@gmail.com>
> + *
> + * This file is part of barebox.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __ASM_DEBUG_LL_LITEX__
> +#define __ASM_DEBUG_LL_LITEX__
> +
> +/** @file
> + *  This File contains declaration for early output support
> + */
> +
> +#include <linux/kconfig.h>
> +
> +#define DEBUG_LL_UART_ADDR	0xf0001000
> +#define UART_RXTX	0x00
> +#define UART_TXFULL	0x04
> +#define UART_RXEMPTY	0x08
> +#define UART_EV_PENDING	0x10
> +#define  UART_EV_RX	(1 << 1)
> +
> +
> +#ifndef __ASSEMBLY__
> +
> +/*
> + * C macros
> + */
> +
> +#include <asm/io.h>
> +
> +static inline void PUTC_LL(char ch)
> +{
> +#ifdef CONFIG_DEBUG_LL
> +	/* wait for space */
> +	while (__raw_readb((u8 *)DEBUG_LL_UART_ADDR + UART_TXFULL))
> +		;
> +
> +	__raw_writeb(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_RXTX);
> +#endif /* CONFIG_DEBUG_LL */
> +}
> +#else /* __ASSEMBLY__ */
> +/*
> + * Macros for use in assembly language code
> + */
> +
> +/*
> + * output a character in a0
> + */
> +.macro	debug_ll_outc_a0
> +#ifdef CONFIG_DEBUG_LL
> +
> +	li	t0, DEBUG_LL_UART_ADDR
> +
> +201:
> +	lbu	t1, UART_TXFULL(t0)	/* uart tx full ? */
> +	andi	t1, t1, 0xff
> +	bnez	t1, 201b		/* try again */
> +
> +	sb	a0, UART_RXTX(t0)	/* write the character */
> +
> +#endif /* CONFIG_DEBUG_LL */
> +.endm
> +
> +/*
> + * output a character
> + */
> +.macro	debug_ll_outc chr
> +#ifdef CONFIG_DEBUG_LL
> +	li	a0, \chr
> +	debug_ll_outc_a0
> +#endif /* CONFIG_DEBUG_LL */
> +.endm
> +
> +/*
> + * check character in input buffer
> + * return value:
> + *  v0 = 0   no character in input buffer
> + *  v0 != 0  character in input buffer
> + */
> +.macro	debug_ll_tstc
> +#ifdef CONFIG_DEBUG_LL
> +	li	t0, DEBUG_LL_UART_ADDR
> +
> +	/* get line status and check for data present */
> +	lbu	s0, UART_RXEMPTY(t0)
> +	bnez    s0, 243f
> +	li	s0, 1
> +	j	244f
> +243:	li	s0, 0
> +244:	nop
> +#endif /* CONFIG_DEBUG_LL */
> +.endm
> +
> +/*
> + * get character to v0
> + */
> +.macro	debug_ll_getc
> +#ifdef CONFIG_DEBUG_LL
> +
> +204:
> +	debug_ll_tstc
> +
> +	/* try again */
> +	beqz	s0, 204b
> +
> +	/* read a character */
> +	lb	s0, UART_RXTX(t0)
> +	li      t1, UART_EV_RX
> +	sb	t1, UART_EV_PENDING(t0)
> +
> +#endif /* CONFIG_DEBUG_LL */
> +.endm
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* __ASM_DEBUG_LL_LITEX__ */
> diff --git a/common/Kconfig b/common/Kconfig
> index db7cc6713a..cd61b0ef6c 100644
> --- a/common/Kconfig
> +++ b/common/Kconfig
> @@ -1379,6 +1379,10 @@ config DEBUG_SIFIVE
>  	bool "SiFive serial0 port"
>  	depends on SOC_SIFIVE
>  
> 
> 
> 
> +config DEBUG_LITEX
> +	bool "LiteX serial port"
> +	depends on SOC_LITEX
> +
>  endchoice
>  
> 
> 
> 
>  config DEBUG_IMX_UART_PORT
> diff --git a/images/Makefile.riscv b/images/Makefile.riscv
> index c44c683431..24e33f5b11 100644
> --- a/images/Makefile.riscv
> +++ b/images/Makefile.riscv
> @@ -15,3 +15,7 @@ pblb-$(CONFIG_BOARD_HIFIVE) += start_hifive_unmatched start_hifive_unleashed
>  FILE_barebox-hifive-unmatched.img = start_hifive_unmatched.pblb
>  FILE_barebox-hifive-unleashed.img = start_hifive_unleashed.pblb
>  image-$(CONFIG_BOARD_HIFIVE) += barebox-hifive-unmatched.img barebox-hifive-unleashed.img
> +
> +pblb-$(CONFIG_BOARD_LITEX_LINUX) += start_litex_linux
> +FILE_barebox-litex-linux.img = start_litex_linux.pblb
> +image-$(CONFIG_BOARD_LITEX_LINUX) += barebox-litex-linux.img

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
  2021-05-25  7:47   ` Jan Lübbe
@ 2021-05-25  8:52     ` Antony Pavlov
  0 siblings, 0 replies; 19+ messages in thread
From: Antony Pavlov @ 2021-05-25  8:52 UTC (permalink / raw)
  To: Jan Lübbe; +Cc: barebox, Ahmad Fatoum

On Tue, 25 May 2021 09:47:05 +0200
Jan Lübbe <jlu@pengutronix.de> wrote:

> On Tue, 2021-05-25 at 10:19 +0300, Antony Pavlov wrote:
> > LiteX is a Migen-based System on Chip, supporting softcore
> > VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
> > 
> > See https://github.com/enjoy-digital/litex and
> > https://github.com/litex-hub/linux-on-litex-vexriscv
> > for details.
> 
> What are your steps for testing this? We have a few ECPIX-5 here, so we should
> be able to reproduce this.

I use Digilent Arty A7-35T.
Here is listex start banner:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Mar 26 2021 11:00:44
 BIOS CRC passed (3dce0a07)

 Migen git sha1: 3ffd64c
 LiteX git sha1: 58701cc4

--=============== SoC ==================--
CPU:            VexRiscv SMP-LINUX @ 100MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            64KiB
SRAM:           8KiB
L2:             0KiB
SDRAM:          262144KiB 16-bit @ 800MT/s (CL-6 CWL-5)


Here are my steps to run barebox:

1. compile barebox/images/barebox-litex-linux.img;
2. set up your tftp-server (192.168.8.100);
   connect Arty board via ethernet to tftp-server;
3. copy barebox-litex-linux.img to boot.bin in your tftp-server root dir;
4. burn litex bitstream into FPGA; 
Litex bios will try to boot from tftp:


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
             Timeout
Booting from flash...
Error: Invalid image length 0xffffffff
Booting from SDCard in SD-Mode...
Booting from boot.json...
Booting from boot.bin...
SDCard boot failed.
Booting from network...
Local IP: 192.168.8.50
Remote IP: 192.168.8.100
Booting from boot.json...
Booting from boot.bin...
Copying boot.bin to 0x40000000... (515567 bytes)
Executing booted program at 0x40000000

--============= Liftoff! ===============--
>riscv-timer riscv-timer: running at 100000000 Hz
Switch to console [cs0]


barebox 2021.05.0-00097-g95181d249a-dirty #1 Tue May 25 10:16:07 MSK 2021


Board: LiteX VexRiscV-SoC-Linux
riscv-timer riscv-timer: running at 100000000 Hz
eth0: got preset MAC address: d8:89:f0:4e:00:10
mdio_bus: miibus0: probed
liteeth f0009000.mac@f0009000.of: liteeth driver registered
m25p80 w25q128@00: n25q128a13 (16384 Kbytes)
netconsole: registered as netconsole-1
malloc space: 0x4eeffc80 -> 0x4fdffc7f (size 15 MiB)

Hit any to stop autoboot:    2
barebox@LiteX VexRiscV-SoC-Linux:/

> 
> Regards,
> Jan
> 
> > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > ---
> >  arch/riscv/Kconfig.socs                  |  14 +++
> >  arch/riscv/boards/Makefile               |   1 +
> >  arch/riscv/boards/litex-linux/Makefile   |   3 +
> >  arch/riscv/boards/litex-linux/lowlevel.c |  22 ++++
> >  arch/riscv/dts/Makefile                  |   1 +
> >  arch/riscv/dts/litex-linux.dts           |  92 +++++++++++++++++
> >  arch/riscv/dts/litex_soc_linux.dtsi      |  49 +++++++++
> >  arch/riscv/include/asm/debug_ll.h        |   3 +
> >  arch/riscv/include/asm/debug_ll_litex.h  | 123 +++++++++++++++++++++++
> >  common/Kconfig                           |   4 +
> >  images/Makefile.riscv                    |   4 +
> >  11 files changed, 316 insertions(+)
> > 
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 67d19caeb3..3ae66776f0 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -42,4 +42,18 @@ config BOARD_HIFIVE
> >  
> > 
> > 
> > 
> >  endif
> >  
> > 
> > 
> > 
> > +config SOC_LITEX
> > +	bool "LiteX SoCs"
> > +	depends on ARCH_RV32I
> > +	select HAS_ASM_DEBUG_LL
> > +	select HAS_NMON
> > +	select USE_COMPRESSED_DTB
> > +	select RISCV_TIMER
> > +
> > +config BOARD_LITEX_LINUX
> > +	bool "litex linux board"
> > +	depends on SOC_LITEX
> > +	select RISCV_M_MODE
> > +	def_bool y
> > +
> >  endmenu
> > diff --git a/arch/riscv/boards/Makefile b/arch/riscv/boards/Makefile
> > index 99f22f32b4..0468871fde 100644
> > --- a/arch/riscv/boards/Makefile
> > +++ b/arch/riscv/boards/Makefile
> > @@ -1,3 +1,4 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >  obj-$(CONFIG_BOARD_ERIZO_GENERIC)	+= erizo/
> >  obj-$(CONFIG_BOARD_HIFIVE)		+= hifive/
> > +obj-$(CONFIG_BOARD_LITEX_LINUX)		+= litex-linux/
> > diff --git a/arch/riscv/boards/litex-linux/Makefile b/arch/riscv/boards/litex-linux/Makefile
> > new file mode 100644
> > index 0000000000..3d217ffe0b
> > --- /dev/null
> > +++ b/arch/riscv/boards/litex-linux/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +
> > +pbl-y += lowlevel.o
> > diff --git a/arch/riscv/boards/litex-linux/lowlevel.c b/arch/riscv/boards/litex-linux/lowlevel.c
> > new file mode 100644
> > index 0000000000..da23ef5633
> > --- /dev/null
> > +++ b/arch/riscv/boards/litex-linux/lowlevel.c
> > @@ -0,0 +1,22 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +
> > +#include <common.h>
> > +#include <asm/barebox-riscv.h>
> > +#include <debug_ll.h>
> > +#include <asm/riscv_nmon.h>
> > +
> > +ENTRY_FUNCTION(start_litex_linux, a0, a1, a2)
> > +{
> > +	extern char __dtb_z_litex_linux_start[];
> > +	void *fdt;
> > +
> > +	barebox_nmon_entry();
> > +
> > +	putc_ll('>');
> > +
> > +	/* On POR, we are running from read-only memory here. */
> > +
> > +	fdt = __dtb_z_litex_linux_start + get_runtime_offset();
> > +
> > +	barebox_riscv_machine_entry(0x40000000, SZ_256M, fdt);
> > +}
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > index 17fdc9445b..683038189f 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -7,5 +7,6 @@ obj- += dummy.o
> >  pbl-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o
> >  pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \
> >                                hifive-unleashed-a00.dtb.o
> > +pbl-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux.dtb.o
> >  
> > 
> > 
> > 
> >  clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
> > diff --git a/arch/riscv/dts/litex-linux.dts b/arch/riscv/dts/litex-linux.dts
> > new file mode 100644
> > index 0000000000..d21fa57e30
> > --- /dev/null
> > +++ b/arch/riscv/dts/litex-linux.dts
> > @@ -0,0 +1,92 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +
> > +#include "litex_soc_linux.dtsi"
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > +	model = "LiteX VexRiscV-SoC-Linux";
> > +	compatible = "litex,vexriscv-soc-linux";
> > +
> > +	aliases {
> > +		rom = &rom;
> > +		sram = &sram;
> > +	};
> > +
> > +	/* ARTY board */
> > +	rom: rom@00000000 {
> > +		compatible = "mmio-sram";
> > +		reg = <0x00000000 0x00008000>;
> > +		read-only;
> > +	};
> > +
> > +	sram: sram@20000000 {
> > +		compatible = "mmio-sram";
> > +		reg = <0x20000000 0x00004000>;
> > +	};
> > +
> > +	main_ram: memory@40000000 {
> > +		device_type = "memory";
> > +		reg = <0x40000000 0x10000000>;
> > +	};
> > +};
> > +
> > +&uart0 {
> > +	status = "okay";
> > +};
> > +
> > +&mac0 {
> > +	status = "okay";
> > +};
> > +
> > +&spi0 {
> > +	status = "okay";
> > +
> > +	spiflash: w25q128@0 {
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "winbond,w25q128", "jedec,spi-nor";
> > +		spi-max-frequency = <104000000>;
> > +		reg = <0>;
> > +	};
> > +};
> > +
> > +/ {
> > +	ledsgpio: gpio@f000a800 {
> > +		compatible = "ti,74175";
> > +		reg = <0xf000a800 0x4>;
> > +		gpio-controller;
> > +		#gpio-cells = <2>;
> > +	};
> > +
> > +	leds {
> > +		compatible = "gpio-leds";
> > +
> > +		ld0 {
> > +			label = "arty:green:ld0";
> > +			gpios = <&ledsgpio 0 GPIO_ACTIVE_HIGH>;
> > +		};
> > +
> > +		ld1 {
> > +			label = "arty:green:ld1";
> > +			gpios = <&ledsgpio 1 GPIO_ACTIVE_HIGH>;
> > +		};
> > +
> > +		ld2 {
> > +			label = "arty:green:ld2";
> > +			gpios = <&ledsgpio 2 GPIO_ACTIVE_HIGH>;
> > +		};
> > +
> > +		ld3 {
> > +			label = "arty:green:ld3";
> > +			gpios = <&ledsgpio 3 GPIO_ACTIVE_HIGH>;
> > +		};
> > +	};
> > +
> > +	swgpio: gpio@f0006000 {
> > +		compatible = "ti,74125";
> > +		reg = <0xf0006000 0x4>;
> > +		gpio-controller;
> > +		#gpio-cells = <2>;
> > +	};
> > +};
> > diff --git a/arch/riscv/dts/litex_soc_linux.dtsi b/arch/riscv/dts/litex_soc_linux.dtsi
> > new file mode 100644
> > index 0000000000..32382b8dc2
> > --- /dev/null
> > +++ b/arch/riscv/dts/litex_soc_linux.dtsi
> > @@ -0,0 +1,49 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +
> > +/dts-v1/;
> > +
> > +/ {
> > +	compatible = "litex,vexriscv-soc-linux";
> > +
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		timebase-frequency = <100000000>; // 100 MHz
> > +
> > +		cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "spinalhdl,vexriscv", "riscv";
> > +			reg = <0>;
> > +		};
> > +	};
> > +
> > +	uart0: serial@f0001000 {
> > +		compatible = "litex,uart";
> > +		reg = <0xf0001000 0x18>;
> > +		status = "disabled";
> > +	};
> > +
> > +	mac0: mac@f0009000 {
> > +		compatible = "litex,liteeth";
> > +		reg = <0xf0009000 0x7c /* base */
> > +			0xf0009800 0x0a /* mdio_base */
> > +			0xb0000000 0x2000>; /* buf_base */
> > +		tx-fifo-depth = <2>;
> > +		rx-fifo-depth = <2>;
> > +		status = "disabled";
> > +	};
> > +
> > +	spi0: spi@f000b800 {
> > +		compatible = "litex,spiflash";
> > +
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		reg = <0xf000b800 0x100>;
> > +		status = "disabled";
> > +	};
> > +};
> > diff --git a/arch/riscv/include/asm/debug_ll.h b/arch/riscv/include/asm/debug_ll.h
> > index 6904460af9..050a1412d1 100644
> > --- a/arch/riscv/include/asm/debug_ll.h
> > +++ b/arch/riscv/include/asm/debug_ll.h
> > @@ -37,6 +37,9 @@ static inline void PUTC_LL(char ch)
> >  
> > 
> > 
> > 
> >  	writel(ch, uart0);
> >  }
> > +#elif defined CONFIG_DEBUG_LITEX
> > +
> > +#include <asm/debug_ll_litex.h>
> >  
> > 
> > 
> > 
> >  #endif
> >  
> > 
> > 
> > 
> > diff --git a/arch/riscv/include/asm/debug_ll_litex.h b/arch/riscv/include/asm/debug_ll_litex.h
> > new file mode 100644
> > index 0000000000..2fcdd9b0ec
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/debug_ll_litex.h
> > @@ -0,0 +1,123 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2019 Antony Pavlov <antonynpavlov@gmail.com>
> > + *
> > + * This file is part of barebox.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + */
> > +
> > +#ifndef __ASM_DEBUG_LL_LITEX__
> > +#define __ASM_DEBUG_LL_LITEX__
> > +
> > +/** @file
> > + *  This File contains declaration for early output support
> > + */
> > +
> > +#include <linux/kconfig.h>
> > +
> > +#define DEBUG_LL_UART_ADDR	0xf0001000
> > +#define UART_RXTX	0x00
> > +#define UART_TXFULL	0x04
> > +#define UART_RXEMPTY	0x08
> > +#define UART_EV_PENDING	0x10
> > +#define  UART_EV_RX	(1 << 1)
> > +
> > +
> > +#ifndef __ASSEMBLY__
> > +
> > +/*
> > + * C macros
> > + */
> > +
> > +#include <asm/io.h>
> > +
> > +static inline void PUTC_LL(char ch)
> > +{
> > +#ifdef CONFIG_DEBUG_LL
> > +	/* wait for space */
> > +	while (__raw_readb((u8 *)DEBUG_LL_UART_ADDR + UART_TXFULL))
> > +		;
> > +
> > +	__raw_writeb(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_RXTX);
> > +#endif /* CONFIG_DEBUG_LL */
> > +}
> > +#else /* __ASSEMBLY__ */
> > +/*
> > + * Macros for use in assembly language code
> > + */
> > +
> > +/*
> > + * output a character in a0
> > + */
> > +.macro	debug_ll_outc_a0
> > +#ifdef CONFIG_DEBUG_LL
> > +
> > +	li	t0, DEBUG_LL_UART_ADDR
> > +
> > +201:
> > +	lbu	t1, UART_TXFULL(t0)	/* uart tx full ? */
> > +	andi	t1, t1, 0xff
> > +	bnez	t1, 201b		/* try again */
> > +
> > +	sb	a0, UART_RXTX(t0)	/* write the character */
> > +
> > +#endif /* CONFIG_DEBUG_LL */
> > +.endm
> > +
> > +/*
> > + * output a character
> > + */
> > +.macro	debug_ll_outc chr
> > +#ifdef CONFIG_DEBUG_LL
> > +	li	a0, \chr
> > +	debug_ll_outc_a0
> > +#endif /* CONFIG_DEBUG_LL */
> > +.endm
> > +
> > +/*
> > + * check character in input buffer
> > + * return value:
> > + *  v0 = 0   no character in input buffer
> > + *  v0 != 0  character in input buffer
> > + */
> > +.macro	debug_ll_tstc
> > +#ifdef CONFIG_DEBUG_LL
> > +	li	t0, DEBUG_LL_UART_ADDR
> > +
> > +	/* get line status and check for data present */
> > +	lbu	s0, UART_RXEMPTY(t0)
> > +	bnez    s0, 243f
> > +	li	s0, 1
> > +	j	244f
> > +243:	li	s0, 0
> > +244:	nop
> > +#endif /* CONFIG_DEBUG_LL */
> > +.endm
> > +
> > +/*
> > + * get character to v0
> > + */
> > +.macro	debug_ll_getc
> > +#ifdef CONFIG_DEBUG_LL
> > +
> > +204:
> > +	debug_ll_tstc
> > +
> > +	/* try again */
> > +	beqz	s0, 204b
> > +
> > +	/* read a character */
> > +	lb	s0, UART_RXTX(t0)
> > +	li      t1, UART_EV_RX
> > +	sb	t1, UART_EV_PENDING(t0)
> > +
> > +#endif /* CONFIG_DEBUG_LL */
> > +.endm
> > +#endif /* __ASSEMBLY__ */
> > +
> > +#endif /* __ASM_DEBUG_LL_LITEX__ */
> > diff --git a/common/Kconfig b/common/Kconfig
> > index db7cc6713a..cd61b0ef6c 100644
> > --- a/common/Kconfig
> > +++ b/common/Kconfig
> > @@ -1379,6 +1379,10 @@ config DEBUG_SIFIVE
> >  	bool "SiFive serial0 port"
> >  	depends on SOC_SIFIVE
> >  
> > 
> > 
> > 
> > +config DEBUG_LITEX
> > +	bool "LiteX serial port"
> > +	depends on SOC_LITEX
> > +
> >  endchoice
> >  
> > 
> > 
> > 
> >  config DEBUG_IMX_UART_PORT
> > diff --git a/images/Makefile.riscv b/images/Makefile.riscv
> > index c44c683431..24e33f5b11 100644
> > --- a/images/Makefile.riscv
> > +++ b/images/Makefile.riscv
> > @@ -15,3 +15,7 @@ pblb-$(CONFIG_BOARD_HIFIVE) += start_hifive_unmatched start_hifive_unleashed
> >  FILE_barebox-hifive-unmatched.img = start_hifive_unmatched.pblb
> >  FILE_barebox-hifive-unleashed.img = start_hifive_unleashed.pblb
> >  image-$(CONFIG_BOARD_HIFIVE) += barebox-hifive-unmatched.img barebox-hifive-unleashed.img
> > +
> > +pblb-$(CONFIG_BOARD_LITEX_LINUX) += start_litex_linux
> > +FILE_barebox-litex-linux.img = start_litex_linux.pblb
> > +image-$(CONFIG_BOARD_LITEX_LINUX) += barebox-litex-linux.img
> 
> -- 
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 


-- 
Best regards,
  Antony Pavlov

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 05/10] litex serial: add setbrg callback
  2021-05-25  7:36   ` Antony Pavlov
@ 2021-05-25 12:48     ` Ahmad Fatoum
  0 siblings, 0 replies; 19+ messages in thread
From: Ahmad Fatoum @ 2021-05-25 12:48 UTC (permalink / raw)
  To: Antony Pavlov, Sascha Hauer, Marek Czerski; +Cc: barebox

Hello Antony,

On 25.05.21 09:36, Antony Pavlov wrote:
> On Tue, 25 May 2021 10:19:47 +0300
> Antony Pavlov <antonynpavlov@gmail.com> wrote:
> 
> Hi all!
> 
> 
>> From: Marek Czerski <m.czerski@ap-tech.pl>
>>
>> setbrg callback (set baudrate) is needed by the loadx/loady commands.
>> Because litex serial has fixed baudrate the callback only checks if
>> the requested baudrate is the same as the CONFIG_BAUDRATE.
>> ---
>>  drivers/serial/serial_litex.c | 9 ++++++++-
>>  1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/serial/serial_litex.c b/drivers/serial/serial_litex.c
>> index 8562a45ecc..9d35a6e44a 100644
>> --- a/drivers/serial/serial_litex.c
>> +++ b/drivers/serial/serial_litex.c
>> @@ -58,6 +58,13 @@ static int litex_serial_tstc(struct console_device *cdev)
>>  	return !litex_serial_readb(cdev, UART_RXEMPTY);
>>  }
>>  
>> +static int litex_setial_setbaudrate(struct console_device *cdev, int baudrate)
>> +{
>> +	if (baudrate != CONFIG_BAUDRATE)
>> +		return -EINVAL;
>> +	return 0;
>> +}
>> +
> 
> I have sent this patch separately because it need special attention.
> 
> LiteX serial port hardware has fixed baudrate and setbaudrate has no sence.
> On the other hand absent setnbaudrate() litex serial makes impossible 
> to use Y-modem data trasfer.
> 
> I don't like CONFIG_BAUDRATE here. Can we use 
> 
> 	if (baudrate != cdev->baudrate)
> 		return -EINVAL;
> 	return 0;
> 
> instead?
> 
> Please comment!

There are other consoles (efi, linux, virtio) that don't support baud rate
setting either, so I think it makes sense to solve this outside of the
individual console drivers.

One way to go about it is move


if (cdev->baudrate == baudrate)

        return 0;

in common/console.c up. Then setting baud rate to the preconfigured value
would succeed everywhere.

> To: Ahmad
> It looks like CONFIG_BAUDRATE is a one more global defconfig parameter
> that complicates "one defconfig for all RISC-V boards" approach.

It's not a deal breaker, users can still use the environment for fine-grained
configuration of the baud rate on a per board basis if they indeed want to
ship the same barebox configuration for LiteX and something else.

The idea of one-defconfig-for-all is that we don't introduce unneeded mutually-
exclusive configurations. This is not the case here.

(I know I still owe you some patches, I will try to get those sent out soon-ish)

Cheers,
Ahmad

> 
> P.S. There is typo in litex_seTial_setbaudrate name. I have noted just now.
> It should be fixed of cause.
> 
> 
>>  static int litex_serial_probe(struct device_d *dev)
>>  {
>>  	struct resource *iores;
>> @@ -73,7 +80,7 @@ static int litex_serial_probe(struct device_d *dev)
>>  	cdev->tstc = &litex_serial_tstc;
>>  	cdev->putc = &litex_serial_putc;
>>  	cdev->getc = &litex_serial_getc;
>> -	cdev->setbrg = NULL;
>> +	cdev->setbrg = &litex_setial_setbaudrate;
>>  
>>  	console_register(cdev);
>>  
>> -- 
>> 2.31.1
>>
> 
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree
  2021-05-25  7:19 ` [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree Antony Pavlov
@ 2021-05-25 12:54   ` Ahmad Fatoum
  0 siblings, 0 replies; 19+ messages in thread
From: Ahmad Fatoum @ 2021-05-25 12:54 UTC (permalink / raw)
  To: Antony Pavlov, barebox

Hi,

On 25.05.21 09:19, Antony Pavlov wrote:
> barebox timer-riscv driver supports one of user counters:
> 
>   * 'cycle', counter for RDCYCLE instruction (CSR 0xc00);
>   * 'time', timer for RDTIME instruction (CSR 0xc01).
> 
> At the moment in M-mode timer-riscv uses the 'cycle' counter,
> and in S-mode timer-riscv uses the 'time' timer.
> 
> Alas picorv32 CPU core supports only the 'cycle' counter.
> VexRiscV CPU core in M-mode supports only the 'time' timer.
> 
> This patch makes it possible to use the 'time' timer
> for VexRiscV CPU in M-mode.

It also changes the default for M-Mode from cycle to time.
I can't comment on whether this is ok, I just copied the logic
from Linux.

> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> ---
>  arch/riscv/dts/erizo.dtsi         |  2 ++
>  drivers/clocksource/timer-riscv.c | 24 ++++++++++++------------
>  2 files changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi
> index 228711bd69..4eb92ae6f1 100644
> --- a/arch/riscv/dts/erizo.dtsi
> +++ b/arch/riscv/dts/erizo.dtsi
> @@ -22,6 +22,8 @@
>  
>  		timebase-frequency = <24000000>;
>  
> +		barebox,csr-cycle;
> +
>  		cpu@0 {
>  			device_type = "cpu";
>  			compatible = "cliffordwolf,picorv32", "riscv";
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index cbbe18d9a6..305d1ecea0 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -12,9 +12,8 @@
>  #include <clock.h>
>  #include <asm/timer.h>
>  #include <asm/csr.h>
> -#include <asm/system.h>
>  
> -static u64 notrace riscv_timer_get_count_sbi(void)
> +static u64 notrace riscv_timer_get_count_time(void)
>  {
>  	__maybe_unused u32 hi, lo;
>  
> @@ -29,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void)
>  	return ((u64)hi << 32) | lo;
>  }
>  
> -static u64 notrace riscv_timer_get_count_rdcycle(void)
> +static u64 notrace riscv_timer_get_count_cycle(void)
>  {
>  	__maybe_unused u32 hi, lo;
>  
> @@ -44,24 +43,25 @@ static u64 notrace riscv_timer_get_count_rdcycle(void)
>  	return ((u64)hi << 32) | lo;
>  }
>  
> -static u64 notrace riscv_timer_get_count(void)
> -{
> -	if (riscv_mode() == RISCV_S_MODE)
> -		return riscv_timer_get_count_sbi();
> -	else
> -		return riscv_timer_get_count_rdcycle();
> -}
> -
>  static struct clocksource riscv_clocksource = {
> -	.read		= riscv_timer_get_count,
>  	.mask		= CLOCKSOURCE_MASK(64),
>  	.priority	= 100,
>  };
>  
>  static int riscv_timer_init(struct device_d* dev)
>  {
> +	struct device_node *cpu;
> +
>  	dev_info(dev, "running at %lu Hz\n", riscv_timebase);
>  
> +	cpu = of_find_node_by_path("/cpus");
> +
> +	if (of_property_read_bool(cpu, "barebox,csr-cycle")) {
> +		riscv_clocksource.read = riscv_timer_get_count_cycle;
> +	} else {
> +		riscv_clocksource.read = riscv_timer_get_count_time;
> +	}
> +
>  	riscv_clocksource.mult = clocksource_hz2mult(riscv_timebase, riscv_clocksource.shift);
>  
>  	return init_clock(&riscv_clocksource);
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon
  2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
                   ` (9 preceding siblings ...)
  2021-05-25  7:19 ` [PATCH v3 10/10] RISC-V: add litex_linux_defconfig Antony Pavlov
@ 2021-08-11  8:52 ` Ahmad Fatoum
  2021-08-17 10:16   ` Antony Pavlov
  10 siblings, 1 reply; 19+ messages in thread
From: Ahmad Fatoum @ 2021-08-11  8:52 UTC (permalink / raw)
  To: Antony Pavlov, barebox

Hello Antony,

On 25.05.21 09:19, Antony Pavlov wrote:
> Changes since v2:
> 
>   * rebase on top of master branch (f873c7ff2497) +
>     "RISC-V: extend multi-image to support both S- and M-Mode"
>     (http://lists.infradead.org/pipermail/barebox/2021-May/036086.html).
>   * "litex serial: add setbrg callback" patch by Marek Czerski is added
>     for review;
>   * fix "clocksource: timer-riscv: select CSR from device tree" patch;
>   * change gpio IP-block base addresses in litex dts;
>   * gpio-74xx-mmio uses device_get_match_data() now.
> 
> Changes since v1:
> 
>   * rebased on top of next branch;
>   * new patches are introduced:
>     * clocksource: timer-riscv: select CSR from device tree
>     * RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive
>     * RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n
>   * almost all of Ahmad's notes are fixed (e.g. unused header files inclusions are dropped);
>   * NOT FIXED: gpio-74xx-mmio still uses dev_get_drvdata(), not device_get_match_data()
> 
> Antony Pavlov (9):
>   clocksource: timer-riscv: select CSR from device tree
>   RISC-V: make it possible to run nmon from PBL C code
>   RISC-V: boards: erizo: make it possible to use nmon
>   serial: add litex UART driver
>   gpio: add driver for 74xx-ICs with MMIO access
>   spi: add litex spiflash driver
>   net: add LiteEth driver
>   RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
>   RISC-V: add litex_linux_defconfig
> 
> Marek Czerski (1):
>   litex serial: add setbrg callback

I'd like to give this a try eventually while following:
https://github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the-Acorn-CLE-215

Do you intend to submit a new revision soon? Is it ok for you if I respin
this series?

Cheers,
Ahmad

>  arch/riscv/Kconfig.socs                  |  14 +
>  arch/riscv/boards/Makefile               |   1 +
>  arch/riscv/boards/erizo/lowlevel.c       |   4 +
>  arch/riscv/boards/litex-linux/Makefile   |   3 +
>  arch/riscv/boards/litex-linux/lowlevel.c |  22 ++
>  arch/riscv/boot/Makefile                 |   1 +
>  arch/riscv/boot/nmon_entry.S             |  13 +
>  arch/riscv/configs/litex_linux_defconfig |  76 +++++
>  arch/riscv/dts/Makefile                  |   1 +
>  arch/riscv/dts/erizo.dtsi                |   2 +
>  arch/riscv/dts/litex-linux.dts           |  92 ++++++
>  arch/riscv/dts/litex_soc_linux.dtsi      |  49 +++
>  arch/riscv/include/asm/debug_ll.h        |   3 +
>  arch/riscv/include/asm/debug_ll_litex.h  | 123 ++++++++
>  arch/riscv/include/asm/riscv_nmon.h      |  49 ++-
>  common/Kconfig                           |   4 +
>  drivers/clocksource/timer-riscv.c        |  24 +-
>  drivers/gpio/Kconfig                     |  14 +
>  drivers/gpio/Makefile                    |   1 +
>  drivers/gpio/gpio-74xx-mmio.c            | 165 ++++++++++
>  drivers/net/Kconfig                      |   8 +
>  drivers/net/Makefile                     |   1 +
>  drivers/net/liteeth.c                    | 376 +++++++++++++++++++++++
>  drivers/serial/Makefile                  |   1 +
>  drivers/serial/serial_litex.c            | 103 +++++++
>  drivers/spi/Kconfig                      |   3 +
>  drivers/spi/Makefile                     |   1 +
>  drivers/spi/litex_spiflash.c             | 241 +++++++++++++++
>  images/Makefile.riscv                    |   4 +
>  29 files changed, 1370 insertions(+), 29 deletions(-)
>  create mode 100644 arch/riscv/boards/litex-linux/Makefile
>  create mode 100644 arch/riscv/boards/litex-linux/lowlevel.c
>  create mode 100644 arch/riscv/boot/nmon_entry.S
>  create mode 100644 arch/riscv/configs/litex_linux_defconfig
>  create mode 100644 arch/riscv/dts/litex-linux.dts
>  create mode 100644 arch/riscv/dts/litex_soc_linux.dtsi
>  create mode 100644 arch/riscv/include/asm/debug_ll_litex.h
>  create mode 100644 drivers/gpio/gpio-74xx-mmio.c
>  create mode 100644 drivers/net/liteeth.c
>  create mode 100644 drivers/serial/serial_litex.c
>  create mode 100644 drivers/spi/litex_spiflash.c
> 


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon
  2021-08-11  8:52 ` [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Ahmad Fatoum
@ 2021-08-17 10:16   ` Antony Pavlov
  2021-08-17 10:20     ` Ahmad Fatoum
  0 siblings, 1 reply; 19+ messages in thread
From: Antony Pavlov @ 2021-08-17 10:16 UTC (permalink / raw)
  To: Ahmad Fatoum; +Cc: barebox

On Wed, 11 Aug 2021 10:52:53 +0200
Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:

Hi Ahmad!

> Hello Antony,
> 
> On 25.05.21 09:19, Antony Pavlov wrote:
> > Changes since v2:
> > 
> >   * rebase on top of master branch (f873c7ff2497) +
> >     "RISC-V: extend multi-image to support both S- and M-Mode"
> >     (http://lists.infradead.org/pipermail/barebox/2021-May/036086.html).
> >   * "litex serial: add setbrg callback" patch by Marek Czerski is added
> >     for review;
> >   * fix "clocksource: timer-riscv: select CSR from device tree" patch;
> >   * change gpio IP-block base addresses in litex dts;
> >   * gpio-74xx-mmio uses device_get_match_data() now.
> > 
> > Changes since v1:
> > 
> >   * rebased on top of next branch;
> >   * new patches are introduced:
> >     * clocksource: timer-riscv: select CSR from device tree
> >     * RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive
> >     * RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n
> >   * almost all of Ahmad's notes are fixed (e.g. unused header files inclusions are dropped);
> >   * NOT FIXED: gpio-74xx-mmio still uses dev_get_drvdata(), not device_get_match_data()
> > 
> > Antony Pavlov (9):
> >   clocksource: timer-riscv: select CSR from device tree
> >   RISC-V: make it possible to run nmon from PBL C code
> >   RISC-V: boards: erizo: make it possible to use nmon
> >   serial: add litex UART driver
> >   gpio: add driver for 74xx-ICs with MMIO access
> >   spi: add litex spiflash driver
> >   net: add LiteEth driver
> >   RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
> >   RISC-V: add litex_linux_defconfig
> > 
> > Marek Czerski (1):
> >   litex serial: add setbrg callback
> 
> I'd like to give this a try eventually while following:
> https://github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the-Acorn-CLE-215
> 
> Do you intend to submit a new revision soon? Is it ok for you if I respin
> this series?

Sorry for delay with reply, I was on vacation.

I have just resend litex patchseries v4.
I have tested it with linux binaries from this repo:

   https://github.com/frantony/arty-linux-on-litex-vexriscv-prebuilt

What do you want to respin in the litex patchseries?

-- 
Best regards,
  Antony Pavlov
 
> Cheers,
> Ahmad
> 
> >  arch/riscv/Kconfig.socs                  |  14 +
> >  arch/riscv/boards/Makefile               |   1 +
> >  arch/riscv/boards/erizo/lowlevel.c       |   4 +
> >  arch/riscv/boards/litex-linux/Makefile   |   3 +
> >  arch/riscv/boards/litex-linux/lowlevel.c |  22 ++
> >  arch/riscv/boot/Makefile                 |   1 +
> >  arch/riscv/boot/nmon_entry.S             |  13 +
> >  arch/riscv/configs/litex_linux_defconfig |  76 +++++
> >  arch/riscv/dts/Makefile                  |   1 +
> >  arch/riscv/dts/erizo.dtsi                |   2 +
> >  arch/riscv/dts/litex-linux.dts           |  92 ++++++
> >  arch/riscv/dts/litex_soc_linux.dtsi      |  49 +++
> >  arch/riscv/include/asm/debug_ll.h        |   3 +
> >  arch/riscv/include/asm/debug_ll_litex.h  | 123 ++++++++
> >  arch/riscv/include/asm/riscv_nmon.h      |  49 ++-
> >  common/Kconfig                           |   4 +
> >  drivers/clocksource/timer-riscv.c        |  24 +-
> >  drivers/gpio/Kconfig                     |  14 +
> >  drivers/gpio/Makefile                    |   1 +
> >  drivers/gpio/gpio-74xx-mmio.c            | 165 ++++++++++
> >  drivers/net/Kconfig                      |   8 +
> >  drivers/net/Makefile                     |   1 +
> >  drivers/net/liteeth.c                    | 376 +++++++++++++++++++++++
> >  drivers/serial/Makefile                  |   1 +
> >  drivers/serial/serial_litex.c            | 103 +++++++
> >  drivers/spi/Kconfig                      |   3 +
> >  drivers/spi/Makefile                     |   1 +
> >  drivers/spi/litex_spiflash.c             | 241 +++++++++++++++
> >  images/Makefile.riscv                    |   4 +
> >  29 files changed, 1370 insertions(+), 29 deletions(-)
> >  create mode 100644 arch/riscv/boards/litex-linux/Makefile
> >  create mode 100644 arch/riscv/boards/litex-linux/lowlevel.c
> >  create mode 100644 arch/riscv/boot/nmon_entry.S
> >  create mode 100644 arch/riscv/configs/litex_linux_defconfig
> >  create mode 100644 arch/riscv/dts/litex-linux.dts
> >  create mode 100644 arch/riscv/dts/litex_soc_linux.dtsi
> >  create mode 100644 arch/riscv/include/asm/debug_ll_litex.h
> >  create mode 100644 drivers/gpio/gpio-74xx-mmio.c
> >  create mode 100644 drivers/net/liteeth.c
> >  create mode 100644 drivers/serial/serial_litex.c
> >  create mode 100644 drivers/spi/litex_spiflash.c
> > 
> 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon
  2021-08-17 10:16   ` Antony Pavlov
@ 2021-08-17 10:20     ` Ahmad Fatoum
  0 siblings, 0 replies; 19+ messages in thread
From: Ahmad Fatoum @ 2021-08-17 10:20 UTC (permalink / raw)
  To: Antony Pavlov; +Cc: barebox

On 17.08.21 12:16, Antony Pavlov wrote:
> On Wed, 11 Aug 2021 10:52:53 +0200
> Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
> 
> Hi Ahmad!
> 
>> Hello Antony,
>>
>> On 25.05.21 09:19, Antony Pavlov wrote:
>>> Changes since v2:
>>>
>>>   * rebase on top of master branch (f873c7ff2497) +
>>>     "RISC-V: extend multi-image to support both S- and M-Mode"
>>>     (http://lists.infradead.org/pipermail/barebox/2021-May/036086.html).
>>>   * "litex serial: add setbrg callback" patch by Marek Czerski is added
>>>     for review;
>>>   * fix "clocksource: timer-riscv: select CSR from device tree" patch;
>>>   * change gpio IP-block base addresses in litex dts;
>>>   * gpio-74xx-mmio uses device_get_match_data() now.
>>>
>>> Changes since v1:
>>>
>>>   * rebased on top of next branch;
>>>   * new patches are introduced:
>>>     * clocksource: timer-riscv: select CSR from device tree
>>>     * RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive
>>>     * RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n
>>>   * almost all of Ahmad's notes are fixed (e.g. unused header files inclusions are dropped);
>>>   * NOT FIXED: gpio-74xx-mmio still uses dev_get_drvdata(), not device_get_match_data()
>>>
>>> Antony Pavlov (9):
>>>   clocksource: timer-riscv: select CSR from device tree
>>>   RISC-V: make it possible to run nmon from PBL C code
>>>   RISC-V: boards: erizo: make it possible to use nmon
>>>   serial: add litex UART driver
>>>   gpio: add driver for 74xx-ICs with MMIO access
>>>   spi: add litex spiflash driver
>>>   net: add LiteEth driver
>>>   RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
>>>   RISC-V: add litex_linux_defconfig
>>>
>>> Marek Czerski (1):
>>>   litex serial: add setbrg callback
>>
>> I'd like to give this a try eventually while following:
>> https://github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the-Acorn-CLE-215
>>
>> Do you intend to submit a new revision soon? Is it ok for you if I respin
>> this series?
> 
> Sorry for delay with reply, I was on vacation.

No worries. :)

> 
> I have just resend litex patchseries v4.
> I have tested it with linux binaries from this repo:
> 
>    https://github.com/frantony/arty-linux-on-litex-vexriscv-prebuilt
> 
> What do you want to respin in the litex patchseries?

Just rebase, address feedback and give it a try.

Thanks for the respin. Building and loading linux-on-litex-vexriscv onto
my FPGA worked, so I'll give your series a try as well later.

(What doesn't yet work is use as PCIe endpoint[1]. Still monkey debugging that)

[1]: https://github.com/enjoy-digital/litepcie/issues/54

Cheers,
Ahmad

> 


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2021-08-17 10:22 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree Antony Pavlov
2021-05-25 12:54   ` Ahmad Fatoum
2021-05-25  7:19 ` [PATCH v3 02/10] RISC-V: make it possible to run nmon from PBL C code Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 03/10] RISC-V: boards: erizo: make it possible to use nmon Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 04/10] serial: add litex UART driver Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 05/10] litex serial: add setbrg callback Antony Pavlov
2021-05-25  7:36   ` Antony Pavlov
2021-05-25 12:48     ` Ahmad Fatoum
2021-05-25  7:19 ` [PATCH v3 06/10] gpio: add driver for 74xx-ICs with MMIO access Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 07/10] spi: add litex spiflash driver Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 08/10] net: add LiteEth driver Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support Antony Pavlov
2021-05-25  7:47   ` Jan Lübbe
2021-05-25  8:52     ` Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 10/10] RISC-V: add litex_linux_defconfig Antony Pavlov
2021-08-11  8:52 ` [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Ahmad Fatoum
2021-08-17 10:16   ` Antony Pavlov
2021-08-17 10:20     ` Ahmad Fatoum

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