[RFC PATCH 09/17] RISC-V: board-dt-2nd: migrate to board info entry point

[Ahmad Fatoum <a.fatoum@barebox.org>]

The Linux image header moves into a head of its own, which branches into
the supervisor mode PBL head. That head records the mode and stashes the
hart ID already, so the entry point no longer needs to.

The generic image can't know its UART in advance, so the board init
callback still looks it up by root compatible. The chainload callback
keeps barebox proper clear of QEMU's FDT as before.

Assisted-by: Claude:fable-5.1
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 arch/riscv/boot/Makefile            |  2 +-
 arch/riscv/boot/board-dt-2nd-head.S | 36 ++++++++++++
 arch/riscv/boot/board-dt-2nd.c      | 89 +++++++++++++----------------
 3 files changed, 78 insertions(+), 49 deletions(-)
 create mode 100644 arch/riscv/boot/board-dt-2nd-head.S

diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
index d98adf7f724b..7878d85b3e64 100644
--- a/arch/riscv/boot/Makefile
+++ b/arch/riscv/boot/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 pbl-y += head.o entry.o entry_ll.o uncompress.o
 pbl-y += nmon_entry.o
-pbl-$(CONFIG_BOARD_GENERIC_DT) += board-dt-2nd.o
+pbl-$(CONFIG_BOARD_GENERIC_DT) += board-dt-2nd.o board-dt-2nd-head.o
diff --git a/arch/riscv/boot/board-dt-2nd-head.S b/arch/riscv/boot/board-dt-2nd-head.S
new file mode 100644
index 000000000000..32f84412dcfe
--- /dev/null
+++ b/arch/riscv/boot/board-dt-2nd-head.S
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <linux/linkage.h>
+#include <asm/image.h>
+
+#if __riscv_xlen == 64
+#define IMAGE_LOAD_OFFSET 0x200000 /* Image load offset (2MB) from start of RAM */
+#else
+#define IMAGE_LOAD_OFFSET 0x400000 /* Image load offset (4MB) from start of RAM */
+#endif
+
+/*
+ * Linux RISC-V image header, so barebox-dt-2nd.img boots like a kernel.
+ * The stack grows down from the image start into the load offset.
+ */
+.section .text_image_header_dt_2nd, "ax"
+ENTRY(__dt_2nd_head)
+	/* Relaxation and compressed instructions would shift the fields */
+	.option push
+	.option norelax
+	.option norvc
+	nop				/* code0 */
+	j	1f			/* code1 */
+	.balign	8
+	.dword	IMAGE_LOAD_OFFSET	/* Image load offset from start of RAM */
+	.dword	_barebox_image_size	/* Effective Image size */
+	.dword	__HEAD_FLAGS		/* Kernel flags */
+	.word	RISCV_HEADER_VERSION	/* version */
+	.word	0			/* reserved */
+	.dword	0			/* reserved */
+	.ascii	RISCV_IMAGE_MAGIC	/* magic 1 */
+	.ascii	RISCV_IMAGE_MAGIC2	/* magic 2 */
+	.word	0			/* reserved (PE-COFF offset) */
+	.option pop
+1:
+	j	__barebox_pbl_head_v1_supervisor
+ENDPROC(__dt_2nd_head)
diff --git a/arch/riscv/boot/board-dt-2nd.c b/arch/riscv/boot/board-dt-2nd.c
index a5e82257e269..36c0d5faa984 100644
--- a/arch/riscv/boot/board-dt-2nd.c
+++ b/arch/riscv/boot/board-dt-2nd.c
@@ -4,70 +4,57 @@
 #include <asm/sections.h>
 #include <linux/sizes.h>
 #include <asm/ns16550.h>
-#include <pbl.h>
-#include <fdt.h>
-
-#if __riscv_xlen == 64
-#define IMAGE_LOAD_OFFSET 0x200000 /* Image load offset(2MB) from start of RAM */
-#else
-#define IMAGE_LOAD_OFFSET 0x400000 /* Image load offset(4MB) from start of RAM */
-#endif
-
-/* because we can depend on being loaded at an offset, we can just use
- * our load address as stack top
- */
-#define __barebox_riscv_head() \
-	__barebox_riscv_header("auipc sp, 0", IMAGE_LOAD_OFFSET, \
-			       RISCV_HEADER_VERSION, "RISCV", RISCV_IMAGE_MAGIC2)
-
 #include <asm/barebox-riscv.h>
+#include <pbl.h>
+#include <pbl/entry.h>
+#include <fdt.h>
 
 static void virt_ns16550_putc(void *base, int ch)
 {
-	early_ns16550_putc(ch, base, 0, readb, writeb);
+	early_ns16550_putc(ch, IOMEM(base), 0, readb, writeb);
 }
 
-static void virt_ns16550_init(void)
+static void virt_ns16550_setup(void *base)
 {
-	void __iomem *base = IOMEM(0x10000000);
-
-	early_ns16550_init(base, 3686400 / CONFIG_BAUDRATE, 0, writeb);
-	pbl_set_putc(virt_ns16550_putc, base);
+	early_ns16550_init(IOMEM(base), 3686400 / CONFIG_BAUDRATE, 0, writeb);
 }
 
+static struct pbl_console riscv_virtio_console = {
+	.setup = virt_ns16550_setup,
+	.arg = (void *)0x10000000,
+	.driver = &(struct pbl_console_driver) { virt_ns16550_putc }
+};
+
 static const struct fdt_device_id console_ids[] = {
-	{ .compatible = "riscv-virtio", .data = virt_ns16550_init },
+	{ .compatible = "riscv-virtio", .data = &riscv_virtio_console },
 	{ /* sentinel */ }
 };
 
-static void noinline __noreturn start_dt_2nd_nonnaked(unsigned long hartid,
-						      unsigned long _fdt)
+/* entry_data is the device tree the image was started with, if any */
+static void dt_2nd_bdinit(unsigned long entry_data)
 {
-	unsigned long membase, memsize, endmem, endfdt, barebox_size;
-	struct fdt_header *fdt = (void *)_fdt;
-	void (*pbl_uart_init)(void);
+	struct fdt_header *fdt = (void *)entry_data;
+	const struct pbl_console *console;
 
 	if (!fdt)
 		hang();
 
-	/*
-	 * We need to call this here, as a multiplatform build
-	 * depends on querying mode for riscv_vendor_id()
-	 */
-	riscv_set_flags(RISCV_S_MODE);
+	console = fdt_device_get_match_data(fdt, "/", console_ids);
+	if (console)
+		__pbl_board_info.console = *console;
 
-	relocate_to_current_adr();
-	setup_c();
+	pbl_get_stage()->board_data = fdt;
+}
 
-	pbl_uart_init = fdt_device_get_match_data(fdt, "/", console_ids);
-	if (pbl_uart_init) {
-		pbl_uart_init();
-		putchar('>');
-	}
+static void __noreturn dt_2nd_chainload(void *boarddata)
+{
+	unsigned long membase, memsize, endmem, endfdt, barebox_size;
+	unsigned long boarddata_ul = (unsigned long)boarddata;
+	struct fdt_header *fdt = boarddata;
 
 	fdt_find_mem(fdt, &membase, &memsize);
 	endmem = membase + memsize;
-	endfdt = _fdt + be32_to_cpu(fdt->totalsize);
+	endfdt = boarddata_ul + be32_to_cpu(fdt->totalsize);
 
 	/*
 	 * QEMU likes to place the FDT at the end of RAM, where barebox
@@ -80,13 +67,19 @@ static void noinline __noreturn start_dt_2nd_nonnaked(unsigned long hartid,
 	handoff_data_add_dt(fdt);
 
 	if (riscv_mem_barebox_image(membase, endmem, barebox_size, NULL) < endfdt &&
-	    _fdt < riscv_mem_stack_top(membase, endmem))
-		memsize = ALIGN_DOWN(_fdt - membase, SZ_1M);
+	    boarddata_ul < riscv_mem_stack_top(membase, endmem))
+		memsize = ALIGN_DOWN(boarddata_ul - membase, SZ_1M);
 
-	barebox_riscv_supervisor_entry(membase, memsize, hartid, NULL);
+	/* The head has set the mode and the hart ID in tp already */
+	barebox_riscv_entry(membase, memsize, NULL, RISCV_S_MODE);
 }
 
-ENTRY_FUNCTION(start_dt_2nd, hartid, _fdt, a2)
-{
-	start_dt_2nd_nonnaked(hartid, _fdt);
-}
+/* The console depends on the machine, so dt_2nd_bdinit() looks it up */
+extern char __dt_2nd_head[];
+
+ENTRY_POINT_HEAD(start_dt_2nd, __dt_2nd_head)
+	.soc_type = SOC_TYPE_GENERIC_DT,
+	.second_stage.stacktop = PBL_STACKTOP_BEFORE_BAREBOX,
+	.second_stage.board_init = dt_2nd_bdinit,
+	.second_stage.soc_chainload = dt_2nd_chainload,
+ENTRY_POINT_END
-- 
2.47.3