[RFC PATCH 10/17] RISC-V: hifive: migrate to board info entry point

[Ahmad Fatoum <a.fatoum@barebox.org>]

OpenSBI starts the HiFive images like a kernel, so they use the
supervisor mode head. Both boards hand the first 128M of DRAM to barebox
proper, so that goes into the new SiFive SoC defaults and the boards
only add their built-in device tree.

The '>' is now printed by the stage dispatch.

Assisted-by: Claude:fable-5.1
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 arch/riscv/boards/hifive/lowlevel.c | 30 ++++++++-------------------
 include/mach/sifive/entry.h         | 32 +++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 21 deletions(-)
 create mode 100644 include/mach/sifive/entry.h

diff --git a/arch/riscv/boards/hifive/lowlevel.c b/arch/riscv/boards/hifive/lowlevel.c
index 5e8969bef1da..ab60c7e96a78 100644
--- a/arch/riscv/boards/hifive/lowlevel.c
+++ b/arch/riscv/boards/hifive/lowlevel.c
@@ -1,26 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
-#include <common.h>
-#include <asm/barebox-riscv.h>
-#include <debug_ll.h>
+#include <mach/sifive/entry.h>
 
-static __always_inline void start_hifive(unsigned long hartid, void *fdt)
-{
-	putc_ll('>');
+extern char __dtb_z_hifive_unmatched_a00_start[];
+extern char __dtb_z_hifive_unleashed_a00_start[];
 
-	barebox_riscv_supervisor_entry(0x80000000, SZ_128M, hartid, fdt);
-}
+ENTRY_POINT(FU740, start_hifive_unmatched)
+	.second_stage.board_data = __dtb_z_hifive_unmatched_a00_start,
+ENTRY_POINT_END
 
-ENTRY_FUNCTION(start_hifive_unmatched, a0, a1, a2)
-{
-	extern char __dtb_z_hifive_unmatched_a00_start[];
-
-	start_hifive(a0, __dtb_z_hifive_unmatched_a00_start + get_runtime_offset());
-}
-
-ENTRY_FUNCTION(start_hifive_unleashed, a0, a1, a2)
-{
-	extern char __dtb_z_hifive_unleashed_a00_start[];
-
-	start_hifive(a0, __dtb_z_hifive_unleashed_a00_start + get_runtime_offset());
-}
+ENTRY_POINT(FU540, start_hifive_unleashed)
+	.second_stage.board_data = __dtb_z_hifive_unleashed_a00_start,
+ENTRY_POINT_END
diff --git a/include/mach/sifive/entry.h b/include/mach/sifive/entry.h
new file mode 100644
index 000000000000..04529099dcf4
--- /dev/null
+++ b/include/mach/sifive/entry.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MACH_SIFIVE_ENTRY_H
+#define __MACH_SIFIVE_ENTRY_H
+
+#include <linux/sizes.h>
+#include <pbl/entry.h>
+#include <asm/barebox-riscv.h>
+
+#define SIFIVE_DRAM_BASE	0x80000000
+
+/*
+ * OpenSBI starts the image in supervisor mode in DRAM. Every board has
+ * at least 128M, boards with more can raise mem_minsz. OpenSBI leaves
+ * the UART set up, so there's no console and the PBL uses DEBUG_LL.
+ */
+#define PBL_SOC_SIFIVE_DEFAULTS(soc)				\
+	.soc_type = SOC_TYPE_##soc,				\
+	.second_stage = {					\
+		.stacktop = SIFIVE_DRAM_BASE + SZ_128M,		\
+		.mem_start = SIFIVE_DRAM_BASE,			\
+		.mem_minsz = SZ_128M,				\
+		.soc_chainload = pbl_stage_barebox_entry,	\
+	}
+
+#define PBL_SOC_FU540_HEAD	__barebox_pbl_head_v1_supervisor
+#define PBL_SOC_FU540_DEFAULTS	PBL_SOC_SIFIVE_DEFAULTS(FU540)
+
+#define PBL_SOC_FU740_HEAD	__barebox_pbl_head_v1_supervisor
+#define PBL_SOC_FU740_DEFAULTS	PBL_SOC_SIFIVE_DEFAULTS(FU740)
+
+#endif
-- 
2.47.3