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From: Ahmad Fatoum <a.fatoum@barebox.org>
To: barebox@lists.infradead.org
Cc: mfe@pengutronix.de, mtr@pengutronix.de,
	Ahmad Fatoum <a.fatoum@barebox.org>
Subject: [RFC PATCH 16/17] RISC-V: litex-linux: migrate to board info entry point
Date: Tue, 27 Oct 2026 08:24:49 +0100	[thread overview]
Message-ID: <20261027074014.3280396-17-a.fatoum@barebox.org> (raw)
In-Reply-To: <20261027074014.3280396-1-a.fatoum@barebox.org>

The LiteX BIOS loads barebox into RAM and starts it in machine mode, so
the image uses the machine mode head and the stage describes the RAM
the old entry point passed to barebox_riscv_machine_entry().

nmon goes into the CPU init callback, which runs before relocation like
the old entry point did. The '>' now comes from the stage dispatch.

Assisted-by: Claude:opus-5.5
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 arch/riscv/boards/litex-linux/lowlevel.c | 30 ++++++++++++++----------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/boards/litex-linux/lowlevel.c b/arch/riscv/boards/litex-linux/lowlevel.c
index 6be3d62e64fb..2d7713cd48fc 100644
--- a/arch/riscv/boards/litex-linux/lowlevel.c
+++ b/arch/riscv/boards/litex-linux/lowlevel.c
@@ -1,22 +1,26 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 #include <common.h>
+#include <pbl/entry.h>
 #include <asm/barebox-riscv.h>
-#include <debug_ll.h>
 #include <asm/riscv_nmon.h>
 
-ENTRY_FUNCTION(start_litex_linux, a0, a1, a2)
+#define LITEX_RAM_BASE	0x40000000
+
+extern char __dtb_z_litex_linux_start[];
+
+static void __prereloc litex_cpu_init(void)
 {
-	extern char __dtb_z_litex_linux_start[];
-	void *fdt;
-
-	/* BIOS will have loaded us into RAM */
-
 	barebox_nmon_entry();
-
-	putc_ll('>');
-
-	fdt = __dtb_z_litex_linux_start + get_runtime_offset();
-
-	barebox_riscv_machine_entry(0x40000000, SZ_256M, fdt);
 }
+
+/* BIOS will have loaded us into RAM */
+ENTRY_POINT_HEAD(start_litex_linux, __barebox_pbl_head_v1_machine)
+	.soc_type = SOC_TYPE_LITEX,
+	.second_stage.stacktop = LITEX_RAM_BASE + SZ_256M,
+	.second_stage.mem_start = LITEX_RAM_BASE,
+	.second_stage.mem_minsz = SZ_256M,
+	.second_stage.board_data = __dtb_z_litex_linux_start,
+	.second_stage.prereloc_cpu_init = litex_cpu_init,
+	.second_stage.soc_chainload = pbl_stage_barebox_entry,
+ENTRY_POINT_END
-- 
2.47.3




  parent reply	other threads:[~2026-10-27  7:45 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-27  7:24 [RFC PATCH 00/17] Switch RISC-V to declarative entry points Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 01/17] asm-generic: add registers.h with a pc_inside() helper Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 02/17] RISC-V: add call_with_stack() helper Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 03/17] RISC-V: implement relocate_to_adr_full() Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 04/17] PBL: add SoC type declaration and handoff support Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 05/17] PBL: introduce board info based entry point framework Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 06/17] PBL: describe the console in the board info and report the stage Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 07/17] RISC-V: make barebox_riscv_entry() non-naked Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 08/17] RISC-V: add PBL heads for the board info stage dispatch Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 09/17] RISC-V: board-dt-2nd: migrate to board info entry point Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 10/17] RISC-V: hifive: " Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 11/17] RISC-V: allow relocating the PBL more than once Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 12/17] RISC-V: nmon: preserve s1-s3 for the caller Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 13/17] RISC-V: beaglev: migrate to board info entry point Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 14/17] RISC-V: allwinner-d1: " Ahmad Fatoum
2026-10-27  7:24 ` [RFC PATCH 15/17] RISC-V: erizo: " Ahmad Fatoum
2026-10-27  7:24 ` Ahmad Fatoum [this message]
2026-10-27  7:24 ` [RFC PATCH 17/17] Documentation: porting: describe the " Ahmad Fatoum

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