[RFC PATCH 15/17] RISC-V: erizo: migrate to board info entry point

[Ahmad Fatoum <a.fatoum@barebox.org>]

Erizo starts barebox from read-only memory on POR, which can be the
boot ROM, the SPI flash or QEMU's BIOS ROM, so the old code copied the
PBL to the start of SDRAM when it wasn't running from there. The stage
names that as relocaddr instead, which is skipped when the image was
loaded there.

DEBUG_LL initialization and nmon go into the CPU init callback, which
runs before relocation, so nmon still runs from where the image was
started and can load a new one into SDRAM. The '>' now comes from the
stage dispatch.

Assisted-by: Claude:opus-5.5
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 arch/riscv/boards/erizo/lowlevel.c | 32 ++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/boards/erizo/lowlevel.c b/arch/riscv/boards/erizo/lowlevel.c
index ab06634bdb8d..ff588b56ee4b 100644
--- a/arch/riscv/boards/erizo/lowlevel.c
+++ b/arch/riscv/boards/erizo/lowlevel.c
@@ -1,22 +1,32 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 #include <common.h>
+#include <pbl/entry.h>
 #include <asm/barebox-riscv.h>
 #include <debug_ll.h>
 #include <asm/riscv_nmon.h>
 
-ENTRY_FUNCTION(start_erizo_generic, a0, a1, a2)
-{
-	extern char __dtb_z_erizo_generic_start[];
-	void *fdt;
+#define ERIZO_SDRAM_BASE	0x80000000
 
+extern char __dtb_z_erizo_generic_start[];
+
+static void __prereloc erizo_cpu_init(void)
+{
 	debug_ll_init();
 	barebox_nmon_entry();
-	putc_ll('>');
-
-	/* On POR, we are running from read-only memory here. */
-
-	fdt = __dtb_z_erizo_generic_start + get_runtime_offset();
-
-	barebox_riscv_machine_entry(0x80000000, SZ_8M, fdt);
 }
+
+/*
+ * On POR, we are running from read-only memory, so the PBL relocates to
+ * the start of SDRAM. It stays in place if it was loaded there.
+ */
+ENTRY_POINT_HEAD(start_erizo_generic, __barebox_pbl_head_v1_machine)
+	.soc_type = SOC_TYPE_ERIZO,
+	.second_stage.stacktop = ERIZO_SDRAM_BASE + SZ_8M,
+	.second_stage.relocaddr = ERIZO_SDRAM_BASE,
+	.second_stage.mem_start = ERIZO_SDRAM_BASE,
+	.second_stage.mem_minsz = SZ_8M,
+	.second_stage.board_data = __dtb_z_erizo_generic_start,
+	.second_stage.prereloc_cpu_init = erizo_cpu_init,
+	.second_stage.soc_chainload = pbl_stage_barebox_entry,
+ENTRY_POINT_END
-- 
2.47.3