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From: Marco Felsch <m.felsch@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 0/6] RISC-V Allwinner D1 Support 2nd Stage Support
Date: Tue, 13 Sep 2022 14:49:48 +0200	[thread overview]
Message-ID: <20220913124954.1346533-1-m.felsch@pengutronix.de> (raw)

Hi,

this small series adds the basic support for the Allwinner sun20i D1
Nezsha board. It is very limited only serial is supported right now.

Patches 1-4 can be applied independently.

Patch 5 may need some more attention since Ahmad told me in person that
not all softcores implementing the vendorid register. Please see the
patch notes on this patch.

Patch 6 adds the support for the D1 board and a detailed description how
to build and flash a bootable image.

Marco Felsch (6):
  RISC-V: cache: fix local_flush_icache_all enabling
  RISC-V: add riscv_vendor_id() support
  RISC-V: import vendorid list from linux
  RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags
  RISC-V: implement cache-management errata for T-Head SoCs
  RISC-V: add Allwinner Sun20i D1 Nezha support

 Documentation/boards/riscv.rst            | 102 +++++++++++++++++
 arch/riscv/Kconfig.socs                   |  16 +++
 arch/riscv/boards/Makefile                |   1 +
 arch/riscv/boards/allwinner-d1/Makefile   |   3 +
 arch/riscv/boards/allwinner-d1/lowlevel.c |  12 ++
 arch/riscv/boot/entry.c                   |   3 +-
 arch/riscv/boot/entry.h                   |   6 +-
 arch/riscv/boot/start.c                   |  13 +--
 arch/riscv/boot/uncompress.c              |   8 +-
 arch/riscv/configs/sun20i_defconfig       | 130 ++++++++++++++++++++++
 arch/riscv/include/asm/cache.h            |  23 +++-
 arch/riscv/include/asm/debug_ll.h         |   5 +
 arch/riscv/include/asm/system.h           |  71 +++++++++---
 arch/riscv/include/asm/vendorid_list.h    |  11 ++
 common/Kconfig                            |   5 +
 images/Makefile.riscv                     |   4 +
 16 files changed, 380 insertions(+), 33 deletions(-)
 create mode 100644 arch/riscv/boards/allwinner-d1/Makefile
 create mode 100644 arch/riscv/boards/allwinner-d1/lowlevel.c
 create mode 100644 arch/riscv/configs/sun20i_defconfig
 create mode 100644 arch/riscv/include/asm/vendorid_list.h

-- 
2.30.2




             reply	other threads:[~2022-09-13 12:51 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13 12:49 Marco Felsch [this message]
2022-09-13 12:49 ` [PATCH 1/6] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-09-13 12:49 ` [PATCH 2/6] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-09-14  8:33   ` Sascha Hauer
2022-09-13 12:49 ` [PATCH 3/6] RISC-V: import vendorid list from linux Marco Felsch
2022-09-13 12:49 ` [PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-09-14  8:33   ` Sascha Hauer
2022-09-14  9:35     ` Marco Felsch
2022-09-13 12:49 ` [PATCH 5/6] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-09-13 12:49 ` [PATCH 6/6] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-09-14  7:43   ` Sascha Hauer
2022-09-14  7:52     ` Marco Felsch
2022-09-14  7:55       ` Sascha Hauer
2022-09-14  8:19         ` Marco Felsch

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