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From: Marco Felsch <m.felsch@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 2/6] RISC-V: add riscv_vendor_id() support
Date: Tue, 13 Sep 2022 14:49:50 +0200	[thread overview]
Message-ID: <20220913124954.1346533-3-m.felsch@pengutronix.de> (raw)
In-Reply-To: <20220913124954.1346533-1-m.felsch@pengutronix.de>

Add the support to query the vendorid which is stored within the
mvendorid register. This register is only accessible from M-Mode so we
need to use the sbi interface if we are running from S-Mode.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/riscv/include/asm/system.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index adf856f9e9..3eb50f63fd 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -5,6 +5,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/sbi.h>
+
 #define RISCV_MODE_MASK 0x3
 enum riscv_mode {
     RISCV_U_MODE	= 0,
@@ -42,6 +44,30 @@ static inline long __riscv_hartid(u32 flags)
 	return hartid;
 }
 
+static inline long __riscv_vendor_id(u32 flags)
+{
+	struct sbiret ret = { .error = -1 };
+	long id;
+
+	switch (__riscv_mode(flags)) {
+	case RISCV_M_MODE:
+		__asm__ volatile("csrr %0, mvendorid\n" : "=r"(id));
+		return id;
+	case RISCV_S_MODE:
+		/*
+		 * We need to use the sbi_ecall() since it can be that we got
+		 * called without a working stack
+		 */
+		ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID,
+				0, 0, 0, 0, 0, 0);
+		if (!ret.error)
+			return ret.value;
+	default:
+	}
+
+	return ret.error;
+}
+
 #ifndef __PBL__
 extern unsigned barebox_riscv_pbl_flags;
 
@@ -54,6 +80,11 @@ static inline long riscv_hartid(void)
 {
 	return __riscv_hartid(barebox_riscv_pbl_flags);
 }
+
+static inline long riscv_vendor_id(void)
+{
+	return __riscv_vendor_id(barebox_riscv_pbl_flags);
+}
 #endif
 
 #endif
-- 
2.30.2




  parent reply	other threads:[~2022-09-13 12:51 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13 12:49 [PATCH 0/6] RISC-V Allwinner D1 Support 2nd Stage Support Marco Felsch
2022-09-13 12:49 ` [PATCH 1/6] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-09-13 12:49 ` Marco Felsch [this message]
2022-09-14  8:33   ` [PATCH 2/6] RISC-V: add riscv_vendor_id() support Sascha Hauer
2022-09-13 12:49 ` [PATCH 3/6] RISC-V: import vendorid list from linux Marco Felsch
2022-09-13 12:49 ` [PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-09-14  8:33   ` Sascha Hauer
2022-09-14  9:35     ` Marco Felsch
2022-09-13 12:49 ` [PATCH 5/6] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-09-13 12:49 ` [PATCH 6/6] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-09-14  7:43   ` Sascha Hauer
2022-09-14  7:52     ` Marco Felsch
2022-09-14  7:55       ` Sascha Hauer
2022-09-14  8:19         ` Marco Felsch

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