mail archive of the barebox mailing list
 help / color / mirror / Atom feed
From: Sascha Hauer <sha@pengutronix.de>
To: Marco Felsch <m.felsch@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 2/6] RISC-V: add riscv_vendor_id() support
Date: Wed, 14 Sep 2022 10:33:58 +0200	[thread overview]
Message-ID: <20220914083358.GK12909@pengutronix.de> (raw)
In-Reply-To: <20220913124954.1346533-3-m.felsch@pengutronix.de>

On Tue, Sep 13, 2022 at 02:49:50PM +0200, Marco Felsch wrote:
> +static inline long __riscv_vendor_id(u32 flags)
> +{
> +	struct sbiret ret = { .error = -1 };
> +	long id;
> +
> +	switch (__riscv_mode(flags)) {
> +	case RISCV_M_MODE:
> +		__asm__ volatile("csrr %0, mvendorid\n" : "=r"(id));
> +		return id;
> +	case RISCV_S_MODE:
> +		/*
> +		 * We need to use the sbi_ecall() since it can be that we got
> +		 * called without a working stack
> +		 */
> +		ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID,
> +				0, 0, 0, 0, 0, 0);
> +		if (!ret.error)
> +			return ret.value;
> +	default:
> +	}

arch/riscv/include/asm/system.h:27:2: error: label at end of compound statement

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



  reply	other threads:[~2022-09-14  8:35 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13 12:49 [PATCH 0/6] RISC-V Allwinner D1 Support 2nd Stage Support Marco Felsch
2022-09-13 12:49 ` [PATCH 1/6] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-09-13 12:49 ` [PATCH 2/6] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-09-14  8:33   ` Sascha Hauer [this message]
2022-09-13 12:49 ` [PATCH 3/6] RISC-V: import vendorid list from linux Marco Felsch
2022-09-13 12:49 ` [PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-09-14  8:33   ` Sascha Hauer
2022-09-14  9:35     ` Marco Felsch
2022-09-13 12:49 ` [PATCH 5/6] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-09-13 12:49 ` [PATCH 6/6] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-09-14  7:43   ` Sascha Hauer
2022-09-14  7:52     ` Marco Felsch
2022-09-14  7:55       ` Sascha Hauer
2022-09-14  8:19         ` Marco Felsch

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220914083358.GK12909@pengutronix.de \
    --to=sha@pengutronix.de \
    --cc=barebox@lists.infradead.org \
    --cc=m.felsch@pengutronix.de \
    --subject='Re: [PATCH 2/6] RISC-V: add riscv_vendor_id() support' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox