From: Marco Felsch <m.felsch@pengutronix.de>
To: Sascha Hauer <sha@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags
Date: Wed, 14 Sep 2022 11:35:01 +0200 [thread overview]
Message-ID: <20220914093501.bd6j6sbvdfp4xoak@pengutronix.de> (raw)
In-Reply-To: <20220914083325.GJ12909@pengutronix.de>
On 22-09-14, Sascha Hauer wrote:
> On Tue, Sep 13, 2022 at 02:49:52PM +0200, Marco Felsch wrote:
> > Use the dedicated scratch register for setting the pbl flags. Each mode
> > has it's own scratch register so we are not conflicting with M-mode
> > running firmware e.g. OpenSBI. Using the scratch register has two main
> > advantages:
> > 1st) It can be used in PBL and non-PBL use-case.
> > 2nd) It is not affected by the relocation code.
> >
> > This commit prepares barebox to add support for the special cache ops
> > used by several T-Head CPUs.
> >
> > +static inline void riscv_set_flags(unsigned flags)
> > +{
> > + switch (flags & RISCV_MODE_MASK) {
> > + case RISCV_S_MODE:
> > + __asm__ volatile("csrw sscratch, %0" : : "r"(flags));
> > + break;
> > + case RISCV_M_MODE:
> > + __asm__ volatile("csrw mscratch, %0" : : "r"(flags));
> > + break;
> > + default:
> > + /* Other modes are not implemented yet */
> > + }
>
> Compilation ends in an error here:
>
> arch/riscv/include/asm/system.h:27:2: error: label at end of compound statement
Arg.. I used GCC11 they introduced the support for by commit 8b7a9a249a6
("C Parser: Implement mixing of labels and code."). Do we need to add
warning like: -Wc11-c2x-compat? So at least the developer gets informed?
Regards,
Marco
next prev parent reply other threads:[~2022-09-14 9:43 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-13 12:49 [PATCH 0/6] RISC-V Allwinner D1 Support 2nd Stage Support Marco Felsch
2022-09-13 12:49 ` [PATCH 1/6] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-09-13 12:49 ` [PATCH 2/6] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-09-14 8:33 ` Sascha Hauer
2022-09-13 12:49 ` [PATCH 3/6] RISC-V: import vendorid list from linux Marco Felsch
2022-09-13 12:49 ` [PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-09-14 8:33 ` Sascha Hauer
2022-09-14 9:35 ` Marco Felsch [this message]
2022-09-13 12:49 ` [PATCH 5/6] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-09-13 12:49 ` [PATCH 6/6] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-09-14 7:43 ` Sascha Hauer
2022-09-14 7:52 ` Marco Felsch
2022-09-14 7:55 ` Sascha Hauer
2022-09-14 8:19 ` Marco Felsch
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220914093501.bd6j6sbvdfp4xoak@pengutronix.de \
--to=m.felsch@pengutronix.de \
--cc=barebox@lists.infradead.org \
--cc=sha@pengutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox