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From: Marco Felsch <m.felsch@pengutronix.de>
To: Sascha Hauer <sha@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 6/6] RISC-V: add Allwinner Sun20i D1 Nezha support
Date: Wed, 14 Sep 2022 10:19:28 +0200	[thread overview]
Message-ID: <20220914081928.ty7a4viz2qb7geqt@pengutronix.de> (raw)
In-Reply-To: <20220914075540.GV6477@pengutronix.de>

On 22-09-14, Sascha Hauer wrote:
> On Wed, Sep 14, 2022 at 09:52:37AM +0200, Marco Felsch wrote:
> > On 22-09-14, Sascha Hauer wrote:
> > > On Tue, Sep 13, 2022 at 02:49:54PM +0200, Marco Felsch wrote:
> > > > Add Allwinner sun20i SoC and D1-Nezha board support.
> > > > 
> > > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > > > ---
> > > >  Documentation/boards/riscv.rst            | 102 +++++++++++++++++
> > > >  arch/riscv/Kconfig.socs                   |  16 +++
> > > >  arch/riscv/boards/Makefile                |   1 +
> > > >  arch/riscv/boards/allwinner-d1/Makefile   |   3 +
> > > >  arch/riscv/boards/allwinner-d1/lowlevel.c |  12 ++
> > > >  arch/riscv/configs/sun20i_defconfig       | 130 ++++++++++++++++++++++
> > > >  arch/riscv/include/asm/debug_ll.h         |   5 +
> > > >  common/Kconfig                            |   5 +
> > > >  images/Makefile.riscv                     |   4 +
> > > >  9 files changed, 278 insertions(+)
> > > >  create mode 100644 arch/riscv/boards/allwinner-d1/Makefile
> > > >  create mode 100644 arch/riscv/boards/allwinner-d1/lowlevel.c
> > > >  create mode 100644 arch/riscv/configs/sun20i_defconfig
> > > > 
> > > 
> > > [...]
> > > 
> > > > diff --git a/arch/riscv/configs/sun20i_defconfig b/arch/riscv/configs/sun20i_defconfig
> > > > new file mode 100644
> > > > index 0000000000..157c430723
> > > > --- /dev/null
> > > > +++ b/arch/riscv/configs/sun20i_defconfig
> > > 
> > > I can select all machines built with sifive_defconfig, starfive_defconfig,
> > > sun20i_defconfig and virt64_defconfig in a single config and
> > > successfully build barebox with all these machines.
> > > 
> > > Instead of adding another defconfig we should go into the opposite
> > > direction and consolidate the defconfigs.
> > > 
> > > Maybe a rv32i_defconfig and a rv64i_defconfig would be it.
> > 
> > Good point. One question, do we even have support for rv32i?
> 
> It can be selected in Kconfig and we have defconfigs built with it, so I
> would assume yes.

Yes, you're right. The LiteX and the Erizo are RV32I. So yes, I'm
completely with you to have two defconfigs, one for 32bit and one for
64bit. Should I do that or do you want to merge them?

Regards,
  Marco

> Sascha
> 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 



      reply	other threads:[~2022-09-14  8:21 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13 12:49 [PATCH 0/6] RISC-V Allwinner D1 Support 2nd Stage Support Marco Felsch
2022-09-13 12:49 ` [PATCH 1/6] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-09-13 12:49 ` [PATCH 2/6] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-09-14  8:33   ` Sascha Hauer
2022-09-13 12:49 ` [PATCH 3/6] RISC-V: import vendorid list from linux Marco Felsch
2022-09-13 12:49 ` [PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-09-14  8:33   ` Sascha Hauer
2022-09-14  9:35     ` Marco Felsch
2022-09-13 12:49 ` [PATCH 5/6] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-09-13 12:49 ` [PATCH 6/6] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-09-14  7:43   ` Sascha Hauer
2022-09-14  7:52     ` Marco Felsch
2022-09-14  7:55       ` Sascha Hauer
2022-09-14  8:19         ` Marco Felsch [this message]

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