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From: Sascha Hauer <sha@pengutronix.de>
To: Marco Felsch <m.felsch@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags
Date: Wed, 14 Sep 2022 10:33:25 +0200	[thread overview]
Message-ID: <20220914083325.GJ12909@pengutronix.de> (raw)
In-Reply-To: <20220913124954.1346533-5-m.felsch@pengutronix.de>

On Tue, Sep 13, 2022 at 02:49:52PM +0200, Marco Felsch wrote:
> Use the dedicated scratch register for setting the pbl flags. Each mode
> has it's own scratch register so we are not conflicting with M-mode
> running firmware e.g. OpenSBI. Using the scratch register has two main
> advantages:
>  1st) It can be used in PBL and non-PBL use-case.
>  2nd) It is not affected by the relocation code.
> 
> This commit prepares barebox to add support for the special cache ops
> used by several T-Head CPUs.
> 
> +static inline void riscv_set_flags(unsigned flags)
> +{
> +	switch (flags & RISCV_MODE_MASK) {
> +	case RISCV_S_MODE:
> +		__asm__ volatile("csrw sscratch, %0" : : "r"(flags));
> +		break;
> +	case RISCV_M_MODE:
> +		__asm__ volatile("csrw mscratch, %0" : : "r"(flags));
> +		break;
> +	default:
> +		/* Other modes are not implemented yet */
> +	}

Compilation ends in an error here:

arch/riscv/include/asm/system.h:27:2: error: label at end of compound statement

Sascha

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  reply	other threads:[~2022-09-14  8:34 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13 12:49 [PATCH 0/6] RISC-V Allwinner D1 Support 2nd Stage Support Marco Felsch
2022-09-13 12:49 ` [PATCH 1/6] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-09-13 12:49 ` [PATCH 2/6] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-09-14  8:33   ` Sascha Hauer
2022-09-13 12:49 ` [PATCH 3/6] RISC-V: import vendorid list from linux Marco Felsch
2022-09-13 12:49 ` [PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-09-14  8:33   ` Sascha Hauer [this message]
2022-09-14  9:35     ` Marco Felsch
2022-09-13 12:49 ` [PATCH 5/6] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-09-13 12:49 ` [PATCH 6/6] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-09-14  7:43   ` Sascha Hauer
2022-09-14  7:52     ` Marco Felsch
2022-09-14  7:55       ` Sascha Hauer
2022-09-14  8:19         ` Marco Felsch

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