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From: Marco Felsch <m.felsch@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 3/6] RISC-V: import vendorid list from linux
Date: Tue, 13 Sep 2022 14:49:51 +0200	[thread overview]
Message-ID: <20220913124954.1346533-4-m.felsch@pengutronix.de> (raw)
In-Reply-To: <20220913124954.1346533-1-m.felsch@pengutronix.de>

Import the vendor id list from upstream linux.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/riscv/include/asm/vendorid_list.h | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 arch/riscv/include/asm/vendorid_list.h

diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
new file mode 100644
index 0000000000..cb89af3f07
--- /dev/null
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2021 SiFive
+ */
+#ifndef ASM_VENDOR_LIST_H
+#define ASM_VENDOR_LIST_H
+
+#define SIFIVE_VENDOR_ID	0x489
+#define THEAD_VENDOR_ID		0x5b7
+
+#endif
-- 
2.30.2




  parent reply	other threads:[~2022-09-13 12:51 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13 12:49 [PATCH 0/6] RISC-V Allwinner D1 Support 2nd Stage Support Marco Felsch
2022-09-13 12:49 ` [PATCH 1/6] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-09-13 12:49 ` [PATCH 2/6] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-09-14  8:33   ` Sascha Hauer
2022-09-13 12:49 ` Marco Felsch [this message]
2022-09-13 12:49 ` [PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-09-14  8:33   ` Sascha Hauer
2022-09-14  9:35     ` Marco Felsch
2022-09-13 12:49 ` [PATCH 5/6] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-09-13 12:49 ` [PATCH 6/6] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-09-14  7:43   ` Sascha Hauer
2022-09-14  7:52     ` Marco Felsch
2022-09-14  7:55       ` Sascha Hauer
2022-09-14  8:19         ` Marco Felsch

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