[PATCH 0/9] arm: socfpga: agilex5: rework low level code

[PATCH 0/9] arm: socfpga: agilex5: rework low level code

[Michael Tretter]

The available SDRAM on an Agilex 5 system isn't fixed, but may change
based on the system configuration. If inline ECC is enabled, 1/8 of the
SDRAM is used for checksums. The memory reserved for the TF-A is also
not usable by barebox. Thus, using hard-coded memory limits is not
sufficient even on a board level.

Rework the Agilex 5 low level code to respect the memory configuration
by reading the available memory from the firewall configuration. The
rework also allows moving the entry code from board-specific code to SoC
specific code.

Patch 1 and 2 clean the TF-A loading as preparation.

Patch 3 to 6 clean and fix the setup and read back of the firewall
configuration.

Patch 7 switches the Arrow AXE5-Eagle development board from fixed
memory limits to the memory limits from the firewall configuration.

Patches 8 and 9 extract the now reusable lowlevel code from the
board-specific code.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
Michael Tretter (9):
      arm: socfpga: agilex5: cleanup TF-A loading
      arm: socfgpa: agilex5: remove unused memsize
      arm: socfpga: agilex5: configure firewall with base and size
      arm: socfpga: agilex5: fix read of memory limit
      arm: socfpga: agilex5: fix SDRAM size calculation
      arm: socfpga: agilex5: remove unused declarations
      arm: socfpga: agilex5: read SDRAM limits from firewall
      arm: socfpga: agilex5: add agilex5_barebox_entry
      arm: socfpga: agilex5: add explicit unreachable after TF-A load

 arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 30 +--------------
 arch/arm/mach-socfpga/agilex5-sdram.c       | 27 ++++++-------
 arch/arm/mach-socfpga/atf.c                 | 59 ++++++++++++++++++++++++-----
 include/mach/socfpga/generic.h              |  2 +-
 include/mach/socfpga/soc64-sdram.h          | 36 +++++++++---------
 5 files changed, 82 insertions(+), 72 deletions(-)
---
base-commit: 2f83a1e9e4ecf9f2fe1948550801c27a60769d2b
change-id: 20260416-socfpga-agilex5-sdram-e2a429635bac

Best regards,
-- 
Michael Tretter <m.tretter@pengutronix.de>

[PATCH 1/9] arm: socfpga: agilex5: cleanup TF-A loading

[Michael Tretter]

Use local variables for the bl31 and bl33 address to be able to change
these more easily and consistently.

Print the TF-A memory locations to the logs.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/atf.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-socfpga/atf.c b/arch/arm/mach-socfpga/atf.c
index d0f57d95415e..98460472227e 100644
--- a/arch/arm/mach-socfpga/atf.c
+++ b/arch/arm/mach-socfpga/atf.c
@@ -11,23 +11,25 @@
 
 void __noreturn agilex5_load_and_start_image_via_tfa(unsigned long memsize)
 {
-	unsigned long atf_dest = AGILEX5_ATF_BL31_BASE_ADDR;
-	void __noreturn (*bl31)(void) = (void *)atf_dest;
+	void *bl31 = (void *)AGILEX5_ATF_BL31_BASE_ADDR;
+	void *bl33 = (void *)AGILEX5_ATF_BL33_BASE_ADDR;
 	struct fwobj tfa;
 
-	pr_debug("Load TFA\n");
-
-	memcpy((void *)AGILEX5_ATF_BL33_BASE_ADDR, __image_start, barebox_image_size);
+	pr_debug("copy bl33 to %p from %p (%zu bytes)\n",
+		 bl33, __image_start, barebox_image_size);
+	memcpy(bl33, __image_start, barebox_image_size);
 
 	get_builtin_firmware(agilex5_bl31_bin, &tfa);
 
+	pr_debug("copy bl31 to %p from %p (%zu bytes)\n",
+		 bl31, tfa.data, tfa.size);
 	memcpy(bl31, tfa.data, tfa.size);
 
 	asm volatile("msr sp_el2, %0" : :
-		     "r" (AGILEX5_ATF_BL33_BASE_ADDR - 16) :
+		     "r" (bl33 - 16) :
 		     "cc");
 
-	pr_debug("Jumping to @0x%08lx\n", atf_dest);
-	bl31_entry((uintptr_t)bl31, 0, AGILEX5_ATF_BL33_BASE_ADDR, 0);
+	pr_debug("Jump to bl31 0x%p\n", bl31);
+	bl31_entry((uintptr_t)bl31, 0, (uintptr_t)bl33, 0);
 	__builtin_unreachable();
 }

-- 
2.47.3

[PATCH 2/9] arm: socfgpa: agilex5: remove unused memsize

[Michael Tretter]

The memsize parameter isn't used when loading the TF-A. Furthermore,
using a fixed memory size may be wrong if inline ecc is enabled, because
inline ecc reduces the amount of usable memory.

Remove the parameter to avoid confusion.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 2 +-
 arch/arm/mach-socfpga/atf.c                 | 2 +-
 include/mach/socfpga/generic.h              | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
index 6b158305fdb5..41c1b832a682 100644
--- a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
+++ b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
@@ -63,7 +63,7 @@ static noinline void axe5_eagle_continue(void)
 		socfpga_mailbox_s10_init();
 		socfpga_mailbox_s10_qspi_open();
 
-		agilex5_load_and_start_image_via_tfa(SZ_1G);
+		agilex5_load_and_start_image_via_tfa();
 	}
 
 	fdt = __dtb_z_socfpga_agilex5_axe5_eagle_start;
diff --git a/arch/arm/mach-socfpga/atf.c b/arch/arm/mach-socfpga/atf.c
index 98460472227e..3ad19e33ac94 100644
--- a/arch/arm/mach-socfpga/atf.c
+++ b/arch/arm/mach-socfpga/atf.c
@@ -9,7 +9,7 @@
 #include <mach/socfpga/generic.h>
 #include <mach/socfpga/soc64-regs.h>
 
-void __noreturn agilex5_load_and_start_image_via_tfa(unsigned long memsize)
+void __noreturn agilex5_load_and_start_image_via_tfa(void)
 {
 	void *bl31 = (void *)AGILEX5_ATF_BL31_BASE_ADDR;
 	void *bl33 = (void *)AGILEX5_ATF_BL33_BASE_ADDR;
diff --git a/include/mach/socfpga/generic.h b/include/mach/socfpga/generic.h
index 07add9ed40d6..06768e9ec0a0 100644
--- a/include/mach/socfpga/generic.h
+++ b/include/mach/socfpga/generic.h
@@ -100,7 +100,7 @@ static inline void arria10_watchdog_disable(void) {}
 #endif
 
 int agilex5_clk_init(void);
-void __noreturn agilex5_load_and_start_image_via_tfa(unsigned long memsize);
+void __noreturn agilex5_load_and_start_image_via_tfa(void);
 
 static inline void __udelay(unsigned us)
 {

-- 
2.47.3

[PATCH 3/9] arm: socfpga: agilex5: configure firewall with base and size

[Michael Tretter]

The firewall configuration internally uses the DDR base address and
reserves some space for the TF-A. Pass the base address of the region 0
as a parameter to make it more visible.

Since base is now the base of region 0 instead of the DDR base, the
passed size must now be the size of region 0 instead of the full DDR
size.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/agilex5-sdram.c | 27 +++++++++++----------------
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-socfpga/agilex5-sdram.c b/arch/arm/mach-socfpga/agilex5-sdram.c
index 4e7994985d26..4d95c7b64306 100644
--- a/arch/arm/mach-socfpga/agilex5-sdram.c
+++ b/arch/arm/mach-socfpga/agilex5-sdram.c
@@ -179,20 +179,14 @@ static bool ddr_ecc_dbe_status(void)
 	return false;
 }
 
-static void sdram_set_firewall(phys_size_t hw_size)
+static void sdram_set_firewall(phys_addr_t base, phys_size_t size)
 {
-	phys_size_t value;
+	phys_addr_t limit = base + size - 1;
 	u32 lower, upper;
 
-	value = SOCFPGA_AGILEX5_DDR_BASE;
-	/* Keep first 1MB of SDRAM memory region as secure region when
-	 * using ATF flow, where the ATF code is located.
-	 */
-	value += SZ_1M;
-
 	/* Setting non-secure MPU region base and base extended */
-	lower = lower_32_bits(value);
-	upper = upper_32_bits(value);
+	lower = lower_32_bits(base);
+	upper = upper_32_bits(base);
 	FW_MPU_DDR_SCR_WRITEL(lower, FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE);
 	FW_MPU_DDR_SCR_WRITEL(upper & 0xff, FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT);
 	FW_F2SDRAM_DDR_SCR_WRITEL(lower, FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE);
@@ -203,11 +197,8 @@ static void sdram_set_firewall(phys_size_t hw_size)
 	FW_MPU_DDR_SCR_WRITEL(upper & 0xff, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT);
 
 	/* Setting non-secure MPU limit and limit extended */
-	value = SOCFPGA_AGILEX5_DDR_BASE + hw_size - 1;
-
-	lower = lower_32_bits(value);
-	upper = upper_32_bits(value);
-
+	lower = lower_32_bits(limit);
+	upper = upper_32_bits(limit);
 	FW_MPU_DDR_SCR_WRITEL(lower, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 	FW_MPU_DDR_SCR_WRITEL(upper & 0xff, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 
@@ -327,7 +318,11 @@ int agilex5_ddr_init_full(void)
 		hw_size -= hw_size / 8;
 	pr_debug("%s: %lld MiB\n", io96b_ctrl.ddr_type, hw_size / SZ_1M);
 
-	sdram_set_firewall(hw_size);
+	/*
+	 * Keep first 1MB of SDRAM memory region as secure region when
+	 * using ATF flow, where the ATF code is located.
+	 */
+	sdram_set_firewall(SOCFPGA_AGILEX5_DDR_BASE + SZ_1M, hw_size - SZ_1M);
 
 	/* Firewall setting for MPFE CSR */
 	/* IO96B0_reg */

-- 
2.47.3

[PATCH 4/9] arm: socfpga: agilex5: fix read of memory limit

[Michael Tretter]

FW_MPU_DDR_DMI0_SCR_READL adds the base address to the register address.

Drop it from the caller to avoid adding the base address twice.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 include/mach/socfpga/soc64-sdram.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/mach/socfpga/soc64-sdram.h b/include/mach/socfpga/soc64-sdram.h
index c84cd7f82537..8f367822e869 100644
--- a/include/mach/socfpga/soc64-sdram.h
+++ b/include/mach/socfpga/soc64-sdram.h
@@ -8,6 +8,8 @@
 
 #include <linux/sizes.h>
 
+#include <mach/socfpga/soc64-firewall.h>
+
 struct altera_sdram_plat {
 	void __iomem *mpfe_base_addr;
 	bool dualport;
@@ -192,8 +194,7 @@ static inline resource_size_t agilex5_mpfe_sdram_size(void)
 	u32 lower;
 	resource_size_t mem = 0;
 
-	lower = FW_MPU_DDR_DMI0_SCR_READL(SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS +
-					  FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
+	lower = FW_MPU_DDR_DMI0_SCR_READL(FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 
 	mem = lower;
 

-- 
2.47.3

[PATCH 5/9] arm: socfpga: agilex5: fix SDRAM size calculation

[Michael Tretter]

The FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT is the upper limit of region 0,
which is a memory address instead of the size. Fix the calculation of
the SDRAM size by taking the SDRAM base address into consideration.

While at it, fix the function for memory addresses larger than 32 bits.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 include/mach/socfpga/soc64-sdram.h | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/include/mach/socfpga/soc64-sdram.h b/include/mach/socfpga/soc64-sdram.h
index 8f367822e869..c3eac2c43076 100644
--- a/include/mach/socfpga/soc64-sdram.h
+++ b/include/mach/socfpga/soc64-sdram.h
@@ -189,16 +189,29 @@ void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
 phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat);
 int agilex5_ddr_init_full(void);
 
-static inline resource_size_t agilex5_mpfe_sdram_size(void)
+static inline phys_addr_t agilex5_mpfe_sdram_base(void)
 {
 	u32 lower;
-	resource_size_t mem = 0;
+	u32 upper;
+
+	lower = FW_MPU_DDR_DMI0_SCR_READL(FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE);
+	upper = FW_MPU_DDR_DMI0_SCR_READL(FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT);
+
+	return ((u64)upper << 32) | lower;
+}
+
+static inline resource_size_t agilex5_mpfe_sdram_size(void)
+{
+	resource_size_t limit;
+	u32 lower;
+	u32 upper;
 
 	lower = FW_MPU_DDR_DMI0_SCR_READL(FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
+	upper = FW_MPU_DDR_DMI0_SCR_READL(FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 
-	mem = lower;
+	limit = ((u64)upper << 32) | lower;
 
-	return mem;
+	return limit - agilex5_mpfe_sdram_base() + 1;
 }
 
 #endif /* _SDRAM_SOC64_H_ */

-- 
2.47.3

[PATCH 6/9] arm: socfpga: agilex5: remove unused declarations

[Michael Tretter]

The functions are declared but neither defined nor used. Remove the
declarations to avoid readers' confusion.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 include/mach/socfpga/soc64-sdram.h | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/include/mach/socfpga/soc64-sdram.h b/include/mach/socfpga/soc64-sdram.h
index c3eac2c43076..681afe3bae0e 100644
--- a/include/mach/socfpga/soc64-sdram.h
+++ b/include/mach/socfpga/soc64-sdram.h
@@ -175,18 +175,6 @@ struct altera_sdram_plat {
 #define FW_HMC_ADAPTOR_REG_ADDR			0xf8020004
 #define FW_HMC_ADAPTOR_MPU_MASK			BIT(0)
 
-u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg);
-u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg);
-u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
-		   u32 data, u32 reg);
-u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
-		   u32 reg);
-int emif_clear(struct altera_sdram_plat *plat);
-int emif_reset(struct altera_sdram_plat *plat);
-int poll_hmc_clock_status(void);
-void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
-//void sdram_set_firewall(struct bd_info *bd);
-phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat);
 int agilex5_ddr_init_full(void);
 
 static inline phys_addr_t agilex5_mpfe_sdram_base(void)

-- 
2.47.3

[PATCH 7/9] arm: socfpga: agilex5: read SDRAM limits from firewall

[Michael Tretter]

The hard-coded membase and memsize are not flexible enough for the
configurable SDRAM setup on Agilex 5.

The SZ_1M offset is the result of reserving some memory for the TF-A.
The offset isn't correct anymore, if the reserved area for the TF-A is
changed.

The memory size may change, if the EMIF is configured with inline ECC,
which reserves 1/8 of the memory for checksums and reduces the usable
SDRAM size. Depending on the EMIF configuration, the same board may or
may not use inline ECC.

Since the PBL in EL3 configures the firewall to consider the reserved
area for the TF-A and the reserved memory for ECC checksums, the PBL in
EL1 may read back the configuration to determine the usable memory for
barebox proper.

Add sanity checks on the base address and size to ensure the firewall is
actually configured.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
index 41c1b832a682..4817b3ec2d86 100644
--- a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
+++ b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
@@ -21,6 +21,8 @@ extern char __dtb_z_socfpga_agilex5_axe5_eagle_start[];
 static noinline void axe5_eagle_continue(void)
 {
 	void *fdt;
+	phys_addr_t membase;
+	phys_size_t memsize;
 
 	agilex5_clk_init();
 
@@ -68,7 +70,15 @@ static noinline void axe5_eagle_continue(void)
 
 	fdt = __dtb_z_socfpga_agilex5_axe5_eagle_start;
 
-	barebox_arm_entry(SOCFPGA_AGILEX5_DDR_BASE + SZ_1M, SZ_1G - SZ_1M, fdt);
+	membase = agilex5_mpfe_sdram_base();
+	memsize = agilex5_mpfe_sdram_size();
+
+	if (membase < SOCFPGA_AGILEX5_DDR_BASE || memsize == 0) {
+		pr_err("Invalid firewall configuration\n");
+		hang();
+	}
+
+	barebox_arm_entry(membase, memsize, fdt);
 }
 
 ENTRY_FUNCTION_WITHSTACK(start_socfpga_agilex5_axe5_eagle, AXE5_STACKTOP, r0, r1, r2)

-- 
2.47.3

[PATCH 8/9] arm: socfpga: agilex5: add agilex5_barebox_entry

[Michael Tretter]

Extract the SoC-specific lowlevel entry code from the board-specific
lowlevel entry code to make it reusable with other boards.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 40 +----------------------------
 arch/arm/mach-socfpga/atf.c                 | 40 ++++++++++++++++++++++++++++-
 include/mach/socfpga/generic.h              |  2 +-
 3 files changed, 41 insertions(+), 41 deletions(-)

diff --git a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
index 4817b3ec2d86..fae542e11e89 100644
--- a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
+++ b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
@@ -8,11 +8,6 @@
 #include <mach/socfpga/debug_ll.h>
 #include <mach/socfpga/init.h>
 #include <mach/socfpga/generic.h>
-#include <mach/socfpga/mailbox_s10.h>
-#include <mach/socfpga/soc64-firewall.h>
-#include <mach/socfpga/soc64-regs.h>
-#include <mach/socfpga/soc64-sdram.h>
-#include <mach/socfpga/soc64-system-manager.h>
 
 extern char __dtb_z_socfpga_agilex5_axe5_eagle_start[];
 
@@ -20,10 +15,6 @@ extern char __dtb_z_socfpga_agilex5_axe5_eagle_start[];
 
 static noinline void axe5_eagle_continue(void)
 {
-	void *fdt;
-	phys_addr_t membase;
-	phys_size_t memsize;
-
 	agilex5_clk_init();
 
 	socfpga_uart_setup_ll();
@@ -49,36 +40,7 @@ static noinline void axe5_eagle_continue(void)
 	mdelay(1000);
 	writel(0x410, 0x10c03300);
 
-	if (current_el() == 3) {
-		agilex5_initialize_security_policies();
-		pr_debug("Security policies initialized\n");
-
-		/*
-		 * need to set the bank select enable before the
-		 * agilex5_ddr_init_full() otherwise the serial doesn't show
-		 * anything.
-		 */
-		if (!IS_ENABLED(CONFIG_DEBUG_LL))
-			writel(LCR_BKSE, SOCFPGA_UART0_ADDRESS + LCR);
-		agilex5_ddr_init_full();
-
-		socfpga_mailbox_s10_init();
-		socfpga_mailbox_s10_qspi_open();
-
-		agilex5_load_and_start_image_via_tfa();
-	}
-
-	fdt = __dtb_z_socfpga_agilex5_axe5_eagle_start;
-
-	membase = agilex5_mpfe_sdram_base();
-	memsize = agilex5_mpfe_sdram_size();
-
-	if (membase < SOCFPGA_AGILEX5_DDR_BASE || memsize == 0) {
-		pr_err("Invalid firewall configuration\n");
-		hang();
-	}
-
-	barebox_arm_entry(membase, memsize, fdt);
+	agilex5_barebox_entry(__dtb_z_socfpga_agilex5_axe5_eagle_start);
 }
 
 ENTRY_FUNCTION_WITHSTACK(start_socfpga_agilex5_axe5_eagle, AXE5_STACKTOP, r0, r1, r2)
diff --git a/arch/arm/mach-socfpga/atf.c b/arch/arm/mach-socfpga/atf.c
index 3ad19e33ac94..e3461d01174e 100644
--- a/arch/arm/mach-socfpga/atf.c
+++ b/arch/arm/mach-socfpga/atf.c
@@ -7,9 +7,12 @@
 #include <asm/barebox-arm.h>
 #include <mach/socfpga/atf.h>
 #include <mach/socfpga/generic.h>
+#include <mach/socfpga/mailbox_s10.h>
 #include <mach/socfpga/soc64-regs.h>
+#include <mach/socfpga/soc64-sdram.h>
+#include <mach/socfpga/soc64-system-manager.h>
 
-void __noreturn agilex5_load_and_start_image_via_tfa(void)
+static void __noreturn agilex5_load_and_start_image_via_tfa(void)
 {
 	void *bl31 = (void *)AGILEX5_ATF_BL31_BASE_ADDR;
 	void *bl33 = (void *)AGILEX5_ATF_BL33_BASE_ADDR;
@@ -33,3 +36,38 @@ void __noreturn agilex5_load_and_start_image_via_tfa(void)
 	bl31_entry((uintptr_t)bl31, 0, (uintptr_t)bl33, 0);
 	__builtin_unreachable();
 }
+
+void __noreturn agilex5_barebox_entry(void *fdt)
+{
+	phys_addr_t membase;
+	phys_size_t memsize;
+
+	if (current_el() == 3) {
+		agilex5_initialize_security_policies();
+		pr_debug("Security policies initialized\n");
+
+		/*
+		 * need to set the bank select enable before the
+		 * agilex5_ddr_init_full() otherwise the serial doesn't show
+		 * anything.
+		 */
+		if (!IS_ENABLED(CONFIG_DEBUG_LL))
+			writel(LCR_BKSE, SOCFPGA_UART0_ADDRESS + LCR);
+		agilex5_ddr_init_full();
+
+		socfpga_mailbox_s10_init();
+		socfpga_mailbox_s10_qspi_open();
+
+		agilex5_load_and_start_image_via_tfa();
+	}
+
+	membase = agilex5_mpfe_sdram_base();
+	memsize = agilex5_mpfe_sdram_size();
+
+	if (membase < SOCFPGA_AGILEX5_DDR_BASE || memsize == 0) {
+		pr_err("Invalid firewall configuration\n");
+		hang();
+	}
+
+	barebox_arm_entry(membase, memsize, fdt);
+}
diff --git a/include/mach/socfpga/generic.h b/include/mach/socfpga/generic.h
index 06768e9ec0a0..6c99a17e81f1 100644
--- a/include/mach/socfpga/generic.h
+++ b/include/mach/socfpga/generic.h
@@ -100,7 +100,7 @@ static inline void arria10_watchdog_disable(void) {}
 #endif
 
 int agilex5_clk_init(void);
-void __noreturn agilex5_load_and_start_image_via_tfa(void);
+void __noreturn agilex5_barebox_entry(void *fdt);
 
 static inline void __udelay(unsigned us)
 {

-- 
2.47.3

[PATCH 9/9] arm: socfpga: agilex5: add explicit unreachable after TF-A load

[Michael Tretter]

While agilex5_load_and_start_image_via_tfa() already contains a
__builtin_unreachable(), it's not obvious that the function doesn't
return when looking at agilex5_barebox_entry().

Add __builtin_unreachable() to help the reader.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/atf.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-socfpga/atf.c b/arch/arm/mach-socfpga/atf.c
index e3461d01174e..c7be4e11d2ea 100644
--- a/arch/arm/mach-socfpga/atf.c
+++ b/arch/arm/mach-socfpga/atf.c
@@ -59,6 +59,7 @@ void __noreturn agilex5_barebox_entry(void *fdt)
 		socfpga_mailbox_s10_qspi_open();
 
 		agilex5_load_and_start_image_via_tfa();
+		__builtin_unreachable();
 	}
 
 	membase = agilex5_mpfe_sdram_base();

-- 
2.47.3

Re: [PATCH 0/9] arm: socfpga: agilex5: rework low level code

[Sascha Hauer]

On Thu, 16 Apr 2026 11:48:04 +0200, Michael Tretter wrote:
> The available SDRAM on an Agilex 5 system isn't fixed, but may change
> based on the system configuration. If inline ECC is enabled, 1/8 of the
> SDRAM is used for checksums. The memory reserved for the TF-A is also
> not usable by barebox. Thus, using hard-coded memory limits is not
> sufficient even on a board level.
> 
> Rework the Agilex 5 low level code to respect the memory configuration
> by reading the available memory from the firewall configuration. The
> rework also allows moving the entry code from board-specific code to SoC
> specific code.
> 
> [...]

Applied, thanks!

[1/9] arm: socfpga: agilex5: cleanup TF-A loading
      https://git.pengutronix.de/cgit/barebox/commit/?id=0c29366bb423 (link may not be stable)
[2/9] arm: socfgpa: agilex5: remove unused memsize
      https://git.pengutronix.de/cgit/barebox/commit/?id=0585325d22e1 (link may not be stable)
[3/9] arm: socfpga: agilex5: configure firewall with base and size
      https://git.pengutronix.de/cgit/barebox/commit/?id=3c77c7702144 (link may not be stable)
[4/9] arm: socfpga: agilex5: fix read of memory limit
      https://git.pengutronix.de/cgit/barebox/commit/?id=6c793c193a3c (link may not be stable)
[5/9] arm: socfpga: agilex5: fix SDRAM size calculation
      https://git.pengutronix.de/cgit/barebox/commit/?id=f32b6ba416d6 (link may not be stable)
[6/9] arm: socfpga: agilex5: remove unused declarations
      https://git.pengutronix.de/cgit/barebox/commit/?id=65a993521e70 (link may not be stable)
[7/9] arm: socfpga: agilex5: read SDRAM limits from firewall
      https://git.pengutronix.de/cgit/barebox/commit/?id=db3c90dc335b (link may not be stable)
[8/9] arm: socfpga: agilex5: add agilex5_barebox_entry
      https://git.pengutronix.de/cgit/barebox/commit/?id=a14292c6b54c (link may not be stable)
[9/9] arm: socfpga: agilex5: add explicit unreachable after TF-A load
      https://git.pengutronix.de/cgit/barebox/commit/?id=57419d18bd2f (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>